Registers For Dtp/External Interrupt Circuit; Dtp/Interrupt Factor Register (Eirr); Fig. 16.3 Registers For Dtp/External Interrupt Circuit; Fig. 16.4 Dtp/Interrupt Factor Register (Eirr) - Fujitsu MB90420/5 (A) Series Hardware Manual

MB90420/5 (A) SERIES F

16.4 Registers for DTP/External Interrupt Circuit

The registers for the DTP/external interrupt circuit are shown.
n Registers for DTP/external interrupt circuit
Address
000031 , 30
H H
000033 , 32
H H

16.4.1 DTP/Interrupt Factor Register (EIRR)

The DTP/Interrupt factor register (EIRR) holds and clears the interrupt factor.
n DTP/Interrupt factor register
Address
000031
H
R/W : Both read and write
: Initial value

Table 16-4 Function of Each Bit of DTP/Interrupt Factor Register (EIRR)

Bit Name
bit 15 ER7 to ER0:
bit 14 External interrupt
bit 13 request flag bits
bit 12
bit 11
bit 10
bit 9
bit 8
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
bit 15
DTP/Interrupt factor register (EIRR)
Interrupt request level setting register (ELVR)

Fig. 16.3 Registers for DTP/External Interrupt Circuit

bit 15 bit 14 bit 13 bit1 2 bit 11 bit 10 bit 9 bit 8 bit 7
ER7 ER6 ER5 ER4
R/W R/W R/W R/W R/W R/W R/W R/W R/W
ER7 to
ER0
0
1

Fig. 16.4 DTP/Interrupt Factor Register (EIRR)

• This bit is set to 1 when the edge or level signal selected using the LB7/LA7 bits to
the LB0/LA0 bits of the interrupt requirement level setting register (ELVR) is input to
the DTP/external interrupt pin (interrupt factor is held).
• The interrupt request is output to the CPU when this bit and the corresponding bit
from EN3 to EN0 of the DTP/interrupt enable register (ENIR) are 1.
• When 0 is written to this bit, it is cleared; when 1 is written to this bit, these bits are
not affected.
Note: When output of two or more external interrupt requests is enabled (ENIR: EN3
to EN0 = 1), clear only bits for which the interrupt is accepted by the CPU (bits
from ER7 to ER0 that are set to 1); avoid clearing other bits unconditionally.
Reference: When the EI
corresponding external interrupt request flag bit is cleared automatically.
bit 8 bit 7
DTP/Interrupt enable register (ENIR)
ER3 ER2 ER1 ER0
External Interrupt Request Flag Bit
At Read
The DTP/external interrupt
input is not present.
The DTP/external interrupt
input is present.
Function
2
OS is started and transfer of one data item is completed, the
16-8
bit 0
bit 0 Initial value
ENIR XXXXXXXX
At Write
This bit is cleared.
Operation is not affected.
B