Bclk*, Picclk, And Tck Generic Clock Waveform; System Bus Valid Delay Timings; System Bus Setup And Hold Timings - Intel CELERON 1.10 GHZ Datasheet

Figure 3. BCLK*, PICCLK, and TCK Generic Clock Waveform
CLK
Figure 4. System Bus Valid Delay Timings
Signal
Figure 5. System Bus Setup and Hold Timings
CLK
Signal
Ts = T8, T12, T27 (Setup Time)
Th = T9, T13, T28 (Hold Time)
V = 1.0V for AGTL+ signal group;
Datasheet
0.7V (0.5V*)
T = T5, T25, T34 (Rise Tim e)
r
T = T6, T26, T35 (Fall Tim e)
f
T = T3, T23, T32 (High Tim e)
h
T = T4, T24, T33 (Low Time)
l
T = T1, T22, T31 (BLCK, TCK, PICCLK Period)
p
Note: BCLK is referenced to 0.5 V and 2.0 V. PICCLK is referenced to 0.7 V and 1.7 V.
For S.E.P. and PPGA packages, TCK is referenced to 0.7 V and 1.7 V.
For the FC-PGA package, TCK is referenced to V
CLK
Tx
Tx = T7, T11, T29a, T29b (Valid Delay)
Tpw = T14, T14B, T15 (Pulse Width)
V = 1.0V for AGTL+ signal group;
For S.E.P and PPGA packages, 1.25V for CMOS, APIC and JTAG signal groups
For FC-PGA package, 0.75V for CMOS, APIC and TAP signal groups
For S.E.P. and PPGA packages, 1.25V for APIC and JTAG signal groups
For the FC-PGA package, 0.75V for APIC and TAP signal groups
®
Intel Celeron
t
h
t
r
1.7V (2.0V*)
t
f
t
p
±200m V.
REF
Valid Valid
V
Tpw
Th
Ts
V
Valid
®
Processor up to 1.10 GHz
1.25V
t
l
Tx
49