Table of Contents
Advertisement
4.4
Interlocked MCR
ARM DDI0145B
If the data for an MCR operation is not available inside the ARM9TDMI pipeline during
its first decode cycle, the ARM9TDMI pipeline will interlock for one or more cycles
until the data is available. An example of this is where the register being transferred is
the destination from a preceding LDR instruction. In this situation the MCR instruction
will enter the decode stage of the coprocessor pipeline, and remain there for a number
of cycles before entering the execute stage. Figure 4-4 on page 4-12 gives an example
of an interlocked MCR.
Copyright © 1998, 1999 ARM Limited. All rights reserved.
ARM9TDMI Coprocessor Interface
4-11
Advertisement
Table of Contents
