Table 13-5: S1D13704 Internal Clock Requirements - Epson S1D13704 Technical Manual

Epson Research and Development
Vancouver Design Center
13.6 Clock Requirements
Function
Register Read/Write
Memory Read/Write
Software Power Save
Hardware Power Save
Hardware Functional Specification
Issue Date: 01/02/08
The following table shows what clock is required for which function in the S1D13704.

Table 13-5: S1D13704 Internal Clock Requirements

BCLK
Is required during register accesses. BCLK
can be shut down between accesses: allow
eight BCLK pulses plus 12 MCLK pulses
(8T + 12T ) after the last access
BCLK MCLK
before shutting BCLK off. Allow one BCLK
pulse after starting up BCLK before the next
access
Is required during memory accesses. BCLK
can be shut down between accesses: allow
eight BCLK pulses plus 12 MCLK pulses
(8T + 12T ) after the last access
BCLK MCLK
before shutting BCLK off. Allow one BCLK
pulse after starting up BCLK before the next
access
Required
Not Required
Can be stopped after 128 frames from
entering Software Power Save, i.e. after
REG[03h] bits 1-0 = 11
Can be stopped after 128 frames from
entering Hardware Power Save
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CLKI
Not Required
Required
S1D13704
X26A-A-001-04