Internal Block Diagram; Functional Block Descriptions; Bus Signal Translation; Control Registers - Epson S1D13503 Technical Manual

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3.4 Internal Block Diagram

IOR#, IOW#, IOCS#,
MEMCS#, MEMR#,
MEMW#, BHE#,
AB[19:0]
READY
DB[15:0]

3.5 Functional Block Descriptions

3.5.1 Bus Signal Translation

According to configuration setting VD2, Bus Signal Translation translates MC68000 type MPU signals, or READY type
MPU signals to internal bus interface signals.

3.5.2 Control Registers

The Control Register contains 16 internal control and configuration registers. These registers can be accessed by either
direct-mapping or by using the built-in internal index register.

3.5.3 Sequence Controller

The Sequence Controller generates horizontal and vertical display timings according to the configuration registers settings.

3.5.4 LCD Panel Interface

The LCD Panel Interface performs frame rate modulation and output data pattern formatting for both passive monochrome
and passive color LCD panels.
Hardware Functional Specification
Issue Date: 01/01/29
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Bus Port
Signal Decoder
Translation
Memory
Decoder
Data Bus
Conversion
Timing Generator
Power Save
Oscillator

Figure 6: Internal Block Diagram

Control Registers
Sequence
Controller
Lookup
Table
Address
Generator
Display
Data
MPU/CRT
Formatter
Selector
SRAM Interface
Page 15
LCDENB
UD[3:0]
LCD
LD[3:0]
Panel
LP, YD,
Interface
XSCL,
WF(XSCL2)
S1D13503
X18A-A-001-08