Nec Vr4102 Configuration - Epson S1D13704 Technical Manual

Epson Research and Development
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4.3 NEC VR4102 Configuration

Interfacing to the NEC VR4102™ Microprocessor
Issue Date: 01/02/12
The NEC V 4102 provides the internal address decoding necessary to map to an external
R
LCD controller. Physical address 0A000000h to 0AFFFFFFh (16M bytes) is reserved for
an external LCD controller.
The S1D13704 supports up to 40K bytes of display buffer memory and 32 bytes for internal
registers. Therefore, the S1D13704 will be shadowed over the entire 16M byte memory
range at 64K byte segments. The starting address of the display buffer is 0A000000h and
register 0 of the S1D13704 (REG[00h]) resides at 0A00FFE0h.
The NEC V 4102 has a 16-bit internal register named BCUCNTREG2 located at address
R
0B000002h. It must be set to the value of 0001h to indicate that LCD controller accesses
use a non-inverting data bus.
The 16-bit internal register named BCUCNTREG1, located at address 0B000000h, must
have bit D[13] (ISA/LCD bit) set to 0 to reserve the 16M bytes space, 0A000000h to
0AFFFFFFh, for LCD use and not as ISA bus memory space.
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