C. Characteristics; Cpu Interface Timing; Interface Timing; Figure 7-1: Sh-3 Interface Timing - Epson S1D13504 Technical Manual

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7 A.C. Characteristics

7.1 CPU Interface Timing

7.1.1 SH-3 Interface Timing
CKIO
A[20:0], M/R#
RD/WR#
BS#
CSn#
WEn#
RD#
WAIT#
D[15:0](write)
D[15:0](read)
S1D13504
X19A-A-002-18
Conditions: IO V = 2.7V to 5.5V unless otherwise specified
DD
T = -40 C to 85 C
A
T and T
rise
C = 50pF (Bus / MPU Interface)
L
C = 100pF (LCD Panel Interface)
L
C = 10pF (Display Buffer Interface)
L
C = 10pF (CRT / DAC Interface)
L
t1 t2 t3
t4
t6 t7
t8 t12
t9
t11
t13

Figure 7-1: SH-3 Interface Timing

Note
The SH-3 Wait State Control Register for the area in which the S1D13504 resides must be set to
a non-zero value.
for all inputs must be 5 nsec (10% ~ 90%)
fall
Epson Research and Development

Vancouver Design Center

t5
t10
t12
t14
t15
t16
Hardware Functional Specification
Issue Date: 01/01/30