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Processor Configuration Registers
Table 63.
LSTS - Link Status Register (Sheet 3 of 3)
Default
Bit
Access
Value
3:0
RO
6.2.41
SLOTCAP - Slot Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
PCI Express Slot related registers allow for the support of Hot Plug.
Table 64.
SLOTCAP - Slot Capabilities Register (Sheet 1 of 2)
Default
Bit
Access
31:19
RW-O
18
RW-O
17
RO
16:15
RW-O
®
TM
Intel
Core
i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
August 2010
Document Number: 323178-003
RST/
PWR
0h
Core
Current Link Speed (CLS)
This field indicates the negotiated Link speed of the given PCI
Express Link.Defined encodings are:
0001b 2.5 GT/s PCI Express Link
All other encodings are reserved. The value in this field is
undefined when the Link is not up.
RST/
Value
PWR
0000h
Core
Physical Slot Number (PSN)
Indicates the physical slot number attached to this Port.
BIOS Requirement: This field must be initialized by BIOS to a
value that assigns a slot number that is globally unique within
the chassis.
1b
Core
No Command Completed Support (NCCS)
When set to 1b, this bit indicates that this slot does not
generate software notification when an issued command is
completed by the Hot-Plug Controller. This bit is only permitted
to be set to 1b if the hotplug capable port is able to accept
writes to all fields of the Slot Control register without delay
between successive writes.
0b
Core
Reserved for Electromechanical Interlock Present (EIP)
When set to 1b, this bit indicates that an Electromechanical
Interlock is implemented on the chassis for this slot.
00b
Core
Slot Power Limit Scale (SPLS)
Specifies the scale used for the Slot Power Limit Value.
00:
01:
10:
11:
If this field is written, the link sends a Set_Slot_Power_Limit
message.
Description
0/6/0/PCI
B4-B7h
00040000h
RW-O; RO
32 bits
Description
1.0x
0.1x
0.01x
0.001x
®
®
Celeron
Processor P4505, U3405 Series
Datasheet Addendum
123
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