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Intel 2I640HL Instruction Manual
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Intel 2I640HL Instruction Manual

Intel 2I640HL Instruction Manual

Intel elkhart lake atom x6413e soc cpu, ddr4 sodimm, 3 x lan / hdmi / usb / com / m.2
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Intel Elkhart Lake ATOM® x6413E SoC CPU,
CAUTION
RISK OF EXPLOSION IF BATTERY IS REPLACED
BY AN INCORRECT TYPE.
DISPOSE OF USED BATTERIES ACCORDING
TO THE INSTRUCTIONS
NO. 2I640HL
Release date: SEP. 15. 2023
2I640HL
DDR4 SODIMM,
3 x LAN / HDMI / USB / COM / M.2
Intel Elkhart Lake ATOM® x6413E SoC CPU
Onboard Hailo-8™ edge AI processor
2 x M.2, 3 x LAN, 1 x Nano SIM
USB, COM, Wide Range DC-IN 9~24V
All-In-One SBC
2 x HDMI, eDP,

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Summary of Contents for Intel 2I640HL

  • Page 1 2I640HL Intel Elkhart Lake ATOM® x6413E SoC CPU, DDR4 SODIMM, 3 x LAN / HDMI / USB / COM / M.2 All-In-One SBC Intel Elkhart Lake ATOM® x6413E SoC CPU Onboard Hailo-8™ edge AI processor 2 x HDMI, eDP, 2 x M.2, 3 x LAN, 1 x Nano SIM...

  • Page 2: Table Of Contents

    1-3-1 REMOVING THE SO-DIMM ..................1-4 DIRECTIONS FOR INSTALLING THE M.2 B KEY MINI CARD ........CHAPTER 2 HARDWARE INSTALLATION ..............2-1 DIMENSION-2I640HL ....................2-2 LAYOUT-2I640HL-CONNECTOR AND JUMPER TOP ..........2-2-1 LAYOUT-2I640HL-CONNECTOR AND JUMPER BOT ..........2-3 DIAGRAM-2I640HL TOP ....................2-3-1 DIAGRAM-2I640HL BOT ..................
  • Page 3 STANDARD ........................3-15 SATA INTERFACE ..................... 3-16 NGFF SOCKET ......................3-17 CRFP1: ANTENNA CONTROL 1x4 PIN (1.25mm) WAFER (OEM) ......3-18 CL12. CL22. CL32: LAN LED INDICATOR 1x4 PIN (1.0mm) WAFER (OPTION) ..CHAPTER 4 INTRODUCTION OF BIOS ................ 4-1 ENTER SETUP ......................4-2 BIOS MENU SCREEN &...
  • Page 4 Trademarks Intel is a registered trademark of Intel Corporation. Award is a registered trademark of Award Software, Inc. All other trademarks, products and or product's name mentioned here are for identification purposes only, and may be trademarks and/or registered trademarks of their respective companies or owners.

  • Page 5: Warning

    Warning ! Battery Batteries on board are consumables. The life time of them are not guaranteed. 2. Fanless solution with HDD The specification & limitation of HDD should be considered carefully when the fanless solution is implemented. We will not give further notification in case of changes of product information and manual.

  • Page 6: Hardware Notice Guide

    Hardware Notice Guide 1. Before linking power supply with the motherboard, please attach DC-in adapter to the motherboard first. Then plug the adapter power to AC outlet. Always shut down the computer normally before you move the system unit or remove the power supply from the motherboard.
  • Page 7 Photo 1 Insert Unplug...

  • Page 8: Chapter 1 General Information

    Celeron® (formerly Elkhart Lake ) Series processors & onboard Hailo-8 AI Accelerator. 2I640HL integrated 3 x 2.5 GbE LAN, 6 x USB, 2 x COM Port, 2 x HDMI (or DP) display interface and 2 x M.2 expansion slot offers the ideal platform for graphics performance with integrated IoT features, real-time performance, manageability, and security.

  • Page 9: Major Feature

    Intel® Atom x6413E Processor 1.5GHz / 2.7GHz (Quad Core), Intel® Celeron Processor J6412 2.0GHz / 2.6GHz (Quad Core) Intel® UHD Graphics for 10th Gen Intel® Atom x6413E 500MHz / 750MHz, Intel® Celeron J6412 400MHz / 800MHz Support HDMI 1.4b up to 3840 x 2160at 60Hz and eDP 1.3 2 Lanes up to 1920 x 1080 at 60Hz.

  • Page 10: Specification

    Intel® Celeron Processor J6412 2.0GHz / 2.6GHz (Quad Core) Memory: DDR4 SODIMM slot x 1, up to 32GB Graphics: Intel® UHD Graphics for 10th Gen Intel® Atom x6413E 500MHz / 750MHz, Intel® Celeron J6412 400MHz/800MHz, HDMI 1.4b up to 3840 x 2160at 60Hz and eDP 1.3 2 Lanes up to 1920 x 1080 at 60Hz.

  • Page 11: Installing The So-Dimm

    1-3 Installing the SO-DIMM 1. Align the SO-DIMM with the connector at a 45 degree angle. 2. Press the SO-DIMM into the connector until you hear a click.
  • Page 12 Notices: 1.The connectors are designed to ensure the correct insertion. If you feel resistance, check t h e connectors & golden finger direction, and realign the card. 2. Make sure the retaining clips (on two sides of the slot) lock onto the notches of the card firmly.

  • Page 13: Removing The So-Dimm

    1-3-1 Removing the SO-DIMM 1. Release the SO-DIMM by pulling outward the two retaining clips and the SO-DIMM pops up slightly. 2. Lift the SO-DIMM out of its connector carefully.

  • Page 14: Directions For Installing The M.2 B Key Mini Card

    1-4 Directions for installing the M.2 B Key Mini Card 1. Unscrew the screw on the board 2. Plug in the Mini Card in a 45 angle 3. Gently push down the Mini Card and screw the screw back.

  • Page 15: Chapter 2 Hardware Installation

    Chapter-2 2-1 Dimension-2I640HL 100.5...

  • Page 16: Layout-2I640Hl-Connector And Jumper Top

    2-2 Layout-2I640HL-Connector and Jumper NGFF2 SATA1 NGFF1 JSB1 CBT1 JAT1 CFP1 CIO1 DP1(option) HDMI1 SODIM1 HDMI2 EDP1 CPO1 CPI1 JVL1...

  • Page 17: Layout-2I640Hl-Connector And Jumper Bot

    2-2-1 Layout-2I640HL-Connector and Jumper Nano SIM USB3.1/2.0 USB2.0 USB2.0...

  • Page 18: Diagram-2I640Hl Top

    2-3 Diagram- 2I640HL NGFF2 SATA1 NGFF1 JSB1 CBT1 JAT1 CFP1 CIO1 DP1(option) HDMI1 SODIM1 HDMI2 CPO1 EDP1 JVL1 CPI1...

  • Page 19: Diagram-2I640Hl Bot

    2-3-1 Diagram- 2I640HL Nano SIM USB3.1/2.0 USB2.0 USB2.0...

  • Page 20: Function Map-2I640Hl

    2-3-2 Function MAP- 2I614HL M.2 Bkey 2242/3042 SATA M.2 Bkey 2242 PCIe x1/SATA-Based SSD USB2.0/USB3.0(OEM) PCIe x2-Based USB2.0 SSD/USB2.0 Power IN always ON CMOS DATA Clear Battery Front Panel COM2 COM1 4DI/4DO Display port (option) DDR4 SODIMM eDP Panel SMBus Power Select +5V/+12V out DC-IN +9V~+24V...

  • Page 21: List Of Jumpers

    2-4 List of Jumpers JSB1: CMOS DATA Clear JAT1: Power in always ON function JVL1: eDP panel power select 2-5 Jumper Setting Description A jumper is ON as a closed circuit with a plastic cap covering two pins. A jumper is OFF as an open circuit without the plastic cap.

  • Page 22: Jsb1: Cmos Data Clear

    2-6 JSB1: CMOS DATA Clear A battery must be used to retain the motherboard configuration in CMOS RAM. Close Pin 1 and Pin 2 of JSB1 to store the CMOS data. To clear the CMOS data, please follow the steps as below: 1.

  • Page 23: Jat1: Power In Always On Function

    2-7 JAT1: Power in always ON function JAT1 DESCRIPION *1-2 Disabled Enable NOTE: Power always on function default is disabled. JAT1 Enable *Disabled 2-8 JVL1: eDP panel power select JVL1 DESCRIPION *2-3 +3.3V NOTE: Attention! Check Device Power in spec. JVL1 *+3.3V...

  • Page 24: Chapter 3 Connection

    Chapter-3 Connection This chapter provides all necessary information of the peripheral's connections, switches and indicators. Always power off the board before you install the peripherals. 3-1 List of Connectors CBT1: CMOS Battery in 1x2 pin (1.25mm) wafer CU1: USB 3.1 type A connector CU2: USB 2.0 type A connector CU3:...

  • Page 25: Cmos Battery Connector

    NGFF1: M.2 B key 2242 H=8.5 sockets 75pin NGFF2: M.2 B key 2242 / 3042 H=8.5 sockets 75pin HDMI1: HDMI typeA connector HDMI2: HDMI typeA connector 90º DP1: DisplayPort connector (option) SATA1: SATA connector 7 pin CRFP1: Antenna control 1x4 pin (1.25mm) wafer (OEM) 3-2 CMOS battery connector CBT1: CMOS Battery in 1x2 pin (1.25mm) wafer PIN NO.

  • Page 26: Usb Interface

    3-3 USB Interface CU1: USB 3.1 / 2.0 Type A connector PIN NO. DESCRIPTION PIN NO. DESCRIPTION USB3.0 TX+ USB 2.0 D- USB3.0 TX- USB 2.0 D+ USB3.0 RX+ USB3.0 RX- CU2.CU3: USB 2.0 Type A connector PIN NO. DESCRIPTION PIN NO.
  • Page 27 CU6.CU7.CU8: USB 2.0 1x4 pin (1.25mm) wafer PIN NO. DESCRIPTION PIN NO. DESCRIPTION DATA- DATA+ pin1 CU7 CU8 pin1...

  • Page 28: Lan Interface

    3-4 LAN Interface CL1.CL2.CL3: RJ45 LAN Connector PIN NO. Description PIN NO. Description TD0+/TX+ TD0-/TX- TD1+/RX+ TD2+/NC TD2-/NC TD1-/RX- TD3+/NC TD3-/NC RJ45 LAN Connector-LED define 2.5 Giga / 1000 / 100Mb Connector Speed 100 Mbps 1000 Mbps 2.5 Gbps Indicate Link LED Active LED Link LED...

  • Page 29: Com Interface

    3-5 COM interface CC1.CC2: COM1 / COM2 2x5 pin (2.0mm) wafer RS232 Mode PIN NO. DESCRIPTION PIN NO. DESCRIPTION Note: 1. COM 1/2 Default RS232, RS485 / RS422 by BIOS control. 2. The pin9 RI can be modify to Power to supply device. The power voltage can be set +12V or +5V. The RI change Voltage function set by BOM control.

  • Page 30: Front Panel Pin Header

    3-6 Front Panel Pin Header CFP1: Front Panel 2x5 pin (2.0mm) wafer PIN NO. Description PIN NO. Description Power button pin Power button GND Reset pin Reset GND Power LED- Power LED+ HDD LED- HDD LED+ LAN LED- LAN LED+ CFP1 pin1...

  • Page 31: Digital Input / Output / Watch Dog Time

    3-7 Digital Input / Output / Watch Dog Time CIO1: DIO 0-3 2x5 pin (2.0mm) wafer PIN NO. Description PIN NO. Description DI-0 DO-3 DI-1 DO-2 DI-2 DO-1 DI-3 DO-0 Note: 1. DI pin default pull up 10KΩ to +5V 2.

  • Page 32: Io Device: F75111 Cio Utility

    3-7-1 IO Device: F75111 CIO Utility The Sample code source you can download from http://tprd.info/lexwiki/index.php/IO_Device:F75111_CIO_Utility <Google Drive> Source file: CIO_Utility_v3.0.7.2W_Src Binary file: CIO_Utility_v3.0.7.2W_Bin_x86 CIO_Utility_v3.0.7.2W_Bin_x64 F75113 DLL: F75113.zip <FTP> Source file: CIO_Utility_v3.0.7.2W_Src Binary file: CIO_Utility_v3.0.7.2W_Bin_x86 CIO_Utility_v3.0.7.2W_Bin_x64 F75113 DLL: F75113.zip MB Support List Ivybridge Bay Trail Apollo Lake...
  • Page 33 How to use this Demo Application...
  • Page 34 Attention Please:You must be install vcredist_x86.exe when first time you run the F75111_DIO.exe DEMO AP, The vcredist_x86.exe include all required DLL file. 1. Press the select your test "2i2o", "4i4o", "4i4o*2", "F75111CIO116", "F75113CIO116", "8i+8o", "1i1o" 2. start test, select single mode or looptest...
  • Page 35 F75111 Layout Picture Introduction F75111 Initial Internal F75111 port address (0x9c) define GPIO1X, GPIO2X, GPIO3X to input or output and Enable WDT function pin Set F75111 DI/DO (sample code as below Get Input value/Set output value) DO: InterDigitalOutput(BYTE byteValue)) DI: InterDigitalInput()
  • Page 36 PULSE mode Sample to setting GP33, 32, 31, 30 output 1mS low pulse signal. this->Write_Byte(F75111_INTERNAL_ADDR, GPIO3X_PULSE_CONTROL, 0x00); // This is setting low,Level output this->Write_Byte(F75111_INTERNAL_ADDR, GPIO3X_PULSE_WIDTH_CONTROL, 0x01); // This selects the pulse width to 1mS this->Write_Byte(F75111_INTERNAL_ADDR, GPIO3X_CONTROL_MODE, 0x0F); // This is setting the GP33, 32, 31, 30 to output function. this->Write_Byte(F75111_INTERNAL_ADDR, GPIO3X_Output_Data , 0x0F);...
  • Page 37 Get Input value BYTE F75111::InterDigitalInput() BYTE byteGPIO1X = 0; BYTE byteGPIO3X = 0; BYTE byteData = 0; this->Read_Byte(F75111_INTERNAL_ADDR,GPIO1X_INPUT_DATA,&byteGPIO1X) ; // Get value from GPIO1X this->Read_Byte(F75111_INTERNAL_ADDR,GPIO3X_INPUT_DATA,&byteGPIO3X) ; // Get value from GPIO3X byteGPIO1X = byteGPIO1X & 0xF0; // Mask unuseful value byteGPIO3X = byteGPIO3X &...
  • Page 38 define F75111 pin in F75111.h //-------------------------------------------------------------------------------------------------------------------------------------- #define F75111_INTERNAL_ADDR 0x9C // OnBoard F75111 Chipset #define F75111_EXTERNAL_ADDR 0x6E // External F75111 Chipset //-------------------------------------------------------------------------------------------------------------------------------------- #define F75111_CONFIGURATION 0x03 // Configure GPIO13 to WDT2 Function //-------------------------------------------------------------------------------------------------------------------------------------- #define GPIO1X_CONTROL_MODE 0x10 // Select Output Mode or Input Mode #define GPIO2X_CONTROL_MODE 0x20 // Select GPIO2X Output Mode or Input Mode #define GPIO3X_CONTROL_MODE...
  • Page 39 Introduction F75113 F75113 Layout Picture Base on 75113.Dll API function as below list F75113_API bool _stdcall F75113_Init(); F75113_API BYTE F75113_GetDigital_Low_Input(); //BDI0-BDI7 F75113_API BYTE F75113_GetDigital_High_Input(); //BDI8-BDI15 F75113_API void F75113_SetDigital_Low_Output(BYTE byteValue); //BDO0-BDO7 F75113_API void F75113_SetDigital_High_Output(BYTE byteValue); //BDO8-BDO15 F75113_API void F75113_SetWDT_Enable(BYTE byteTimer); //For the F75113 on board F75113_API void F75113_SetWDT_Disable();...

  • Page 40: Io Device:f75111 Cio Utility Under Linux

    3-7-2 IO Device:F75111 CIO Utility under Linux http://tprd.info/lexwiki/index.php/IO_Device:F75111_CIO_Utility_under_Linux The Sample code source you can download from <Google Drive> Source file: CIO_Utility_v3.2.1L_Src Binary file: CIO_Utility_v3.2.1L_Bin_x64 <FTP> Source file: CIO_Utility_v3.2.1L_Src Binary file: CIO_Utility_v3.2.1L_Bin_x64 MB Support List Ivybridge Bay Trail Apollo Lake Skylake / Kabylake 1I385A/H 2I610DW/HW 2I847H...
  • Page 41 How to use this Demo Application...
  • Page 42 Before executing the program began, Please switch to the highest authority , continued second F75111 ,chmod 777 and root: \ Platform will detect intel/AMD , if not get SMbus signal show N/A If get SMBUS1 / SMBUS2 F75111 / F75113 will show Sessuce, IC not get will show Fail, Not get SMBUS1 / SMBUS2 signal will show N/A 1.
  • Page 43 F75111 Layout Picture F75111 Layout Picture Introduction Introduction Initial Internal F75111 port address (0x9c) Initial Internal F75111 port address (0x9c) define GPIO1X, GPIO2X, GPIO3X to input or output define GPIO1X, GPIO2X, GPIO3X to input or output and Enable WDT function pin and Enable WDT function pin Set F75111 DI/DO (sample code as below Get Input value / Set output value) Set F75111 DI/DO (sample code as below Get Input value / Set output value)
  • Page 44 Initial internal F75111 void F75111::InitInternalF75111() this->Write_Byte(F75111_INTERNAL_ADDR,GPIO1X_CONTROL_MODE, 0x00); //set GPIO1X to Input function this->Write_Byte(F75111_INTERNAL_ADDR,GPIO3X_CONTROL_MODE, 0x00); //set GPIO3X to Input function this->Write_Byte(F75111_INTERNAL_ADDR,GPIO2X_CONTROL_MODE, 0xFF); //set GPIO2X to Output function this->Write_Byte(F75111_INTERNAL_ADDR,GPIO2X_OUTPUT_DRIVING, 0xFF); //set GPIO2X to Output Drving this->Write_Byte(F75111_INTERNAL_ADDR,F75111_CONFIGURATION, 0x03); //Enable WDT OUT function Set output value void F75111::InterDigitalOutput(BYTE byteValue) BYTE byteData = 0;...
  • Page 45 Get Input value BYTE F75111::InterDigitalInput() BYTE byteGPIO1X = 0; BYTE byteGPIO3X = 0; BYTE byteData = 0; this->Read_Byte(F75111_INTERNAL_ADDR,GPIO1X_INPUT_DATA,&byteGPIO1X) ; // Get value from GPIO1X this->Read_Byte(F75111_INTERNAL_ADDR,GPIO3X_INPUT_DATA,&byteGPIO3X) ; // Get value from GPIO3X byteGPIO1X = byteGPIO1X & 0xF0; // Mask unuseful value byteGPIO3X = byteGPIO3X &...
  • Page 46 define F75111 pin in F75111.h //-------------------------------------------------------------------------------------------------------------------------------------- #define F75111_INTERNAL_ADDR 0x9C // OnBoard F75111 Chipset #define F75111_EXTERNAL_ADDR 0x6E // External F75111 Chipset //-------------------------------------------------------------------------------------------------------------------------------------- #define F75111_CONFIGURATION 0x03 // Configure GPIO13 to WDT2 Function //-------------------------------------------------------------------------------------------------------------------------------------- #define GPIO1X_CONTROL_MODE 0x10 // Select Output Mode or Input Mode #define GPIO2X_CONTROL_MODE 0x20 // Select GPIO2X Output Mode or Input Mode #define GPIO3X_CONTROL_MODE...

  • Page 47: Io Device:f75111 Cio Utility Console Under Linux

    3-7-3 IO Device:F75111 CIO Utility Console under linux http://tprd.info/lexwiki/index.php/IO_Device:F75111_CIO_Utility_Console_under_linux The Sample code source you can download from <Google Drive> Source file: CIO_Utility_Console_v1.4L_Src Binary file: CIO_Utility_Console_v1.4L_Bin <FTP> Source file: CIO_Utility_Console_v1.4L_Src Binary file: CIO_Utility_Console_v1.4L_Bin MB Support List Ivybridge BayTrail Apollo Lake Skylake/Kabylake Card 2I847H 1I385A/H...
  • Page 48 F75111 Layout Picture Introduction Initial Internal F75111 port address (0x9c) define GPIO1X, GPIO2X, GPIO3X to input or output and Enable WDT function pin Set F75111 DI/DO ( sample code as below Get Input value / Set output value ) DO: InterDigitalOutput (BYTE byteValue)) DI: InterDigitalInput() PULSE mode Sample to setting GP33, 32, 31, 30 output 1mS low pulse signal.
  • Page 49 Initial internal F75111 void F75111::InitInternalF75111() this->Write_Byte(F75111_INTERNAL_ADDR,GPIO1X_CONTROL_MODE, 0x00); //set GPIO1X to Input function this->Write_Byte(F75111_INTERNAL_ADDR,GPIO3X_CONTROL_MODE, 0x00); //set GPIO3X to Input function this->Write_Byte(F75111_INTERNAL_ADDR,GPIO2X_CONTROL_MODE, 0xFF); //set GPIO2X to Output function this->Write_Byte(F75111_INTERNAL_ADDR,GPIO2X_OUTPUT_DRIVING, 0xFF); //set GPIO2X to Output Drving this->Write_Byte(F75111_INTERNAL_ADDR,F75111_CONFIGURATION, 0x03); //Enable WDT OUT function Set output value void F75111::InterDigitalOutput(BYTE byteValue) BYTE byteData = 0;...
  • Page 50 define F75111 pin in F75111.h //------------------------------------------------------------------------------------------------------------------------------------------------------- #define F75111_INTERNAL_ADDR 0x9C // OnBoard F75111 Chipset #define F75111_EXTERNAL_ADDR 0x6E // External F75111 Chipset //------------------------------------------------------------------------------------------------------------------------------------------------------- #define F75111_CONFIGURATION 0x03 // Configure GPIO13 to WDT2 Function //------------------------------------------------------------------------------------------------------------------------------------------------------- #define GPIO1X_CONTROL_MODE 0x10 // Select Output Mode or Input Mode #define GPIO2X_CONTROL_MODE 0x20...

  • Page 51: Smbus Interface

    3-8 SMBus Interface CO1: SMBus 1x4 pin (1.25mm) wafer PIN NO. DESCRIPTION PIN NO. DESCRIPTION +3.3V SMB-Clock SMB-Data pin1...

  • Page 52: Dc Power Input

    3-9 DC Power Input CPI1: DC Power input 1x4 pin (2.0mm) wafer (RED) PIN NO. DESCRIPTION DC-IN Note: Very important check DC-in Voltage. CPI1 pin1 3-10 DC +12V / +5 Voltage Power Output CPO1: +12V / +5V DC voltage output 1x4 pin (2.0mm) wafer (Black) PIN NO.

  • Page 53: Hdmi1/Hdmi2: Hdmi Type A Connectoer

    3-11 HDMI1 / HDMI2: HDMI type A connector PIN NO. DESCRIPTION PIN NO. DESCRIPTION TMDS DATA2+ TMDS DATA2- TMDS DATA1+ TMDS DATA1- TMDS DATA0+ TMDS DATA0- TMDS CLK+ TMDS CLK- DDC CLOCK DDC DATA H.P. Detect HDMI2 HDMI HDMI1 HDMI...

  • Page 54: Dp1: Displayport Connector (Option)

    3-12 DP1: DisplayPort connector (option) PIN NO. DESCRIPTION PIN NO. DESCRIPTION Lane0+ Lane0- Lane1+ Lane1- Lane2+ Lane2- Lane3+ Lane3- AUX_CH+ AUX_CH- H.P. Detect +3.3V...

  • Page 55: Edp1:Edp Interface 2X10 Pin (1.25Mm) Wafer

    3-13 EDP1: eDP interface 2x10 pin (1.25mm) wafer PIN NO. DESCRIPTION PIN NO. DESCRIPTION Lane-0-DATA- +12V Lane-0-DATA+ +12V Lane-1-DATA- Lane-1-DATA+ Backlight Enable PWM dimming I2C Clock +LCD (5V or 3.3V) I2C Data +LCD (5V or 3.3V) eDP Aux+ +LCD (5V or 3.3V) eDP Aux- EDP_HPD Note:...

  • Page 56: Sim1: Nano Sim Card Push-Push Follow Iso 7816-2 Smart Card

    3-14 SIM1: Nano SIM Card Push-Push Follow ISO 7816-2 Smart Card Standard. PIN NO. DESCRIPTION PIN NO. DESCRIPTION DATA SIM1 Nano SIM 3-15 SATA Interface SATA1: SATA port 1x7 pin Connector PIN NO. DESCRIPTION PIN NO. DESCRIPTION SATA1...

  • Page 57: Ngff Socket

    3-16 NGFF socket NGFF1: PCI Express M.2 B key 2242 H=8.5 sockets 75pin PIN NO. Description PIN NO. Description +3.3V +3.3V FULL_CARD_PWR USB 2.0_P USB 2.0_N M2_LED B Key notch PCIE_5_RX_DN NGFF1 PCIE_5_RX_DP PCIE_5_TX_DN PCIE_5_TX_DP PCIE_4_RX_DN PCIE_4_RX_DP PCIE_4_TX_DN PCIE_4_TX_DP PREST SRCCLKREQ_N PCIE_CLK_N0 PCIE_CLK_P0...
  • Page 58 NGFF2: PCI Express M.2 B key 2242 / 3042 H=8.5 sockets 75pin PIN NO. Description PIN NO. Description +3.3V / +3.7V +3.3V / +3.7V FULL_CARD_PWR USB 2.0_P W_DISABLE_1 USB 2.0_N M2_LED B Key notch W_DISABLE_2 USB31_1_RX_DN SIM_RST_M2 NGFF2 USB31_1_RX_DP SIM_CLK_M2 SIM_DATA_M2 USB31_1_TX_DN SIM_PWR_M2...

  • Page 59: Crfp1: Antenna Control 1X4 Pin (1.25Mm) Wafer (Oem)

    3-17 CRFP1: Antenna control 1x4 pin (1.25mm) wafer (OEM) PIN NO. DESCRIPTION PIN NO. DESCRIPTION ANTCTL1 ANTCTL2 Note: 1. Antenna control by OEM 2. Antenna control with NGFF2 3-18 CL12.CL22.CL32: LAN LED indicator 1x4 pin (1.0mm) wafer (option) PIN NO. DESCRIPTION PIN NO.

  • Page 60: Introduction Of Bios

    Chapter-4 Introduction of BIOS The BIOS is a program located in the Flash Memory on the motherboard. This program is a bridge between motherboard and operating system. When you start the computer, the BIOS program gains control. The BIOS first operates an auto-diagnostic test called POST (Power on Self Test) for all the necessary hardware, it detects the entire hardware devices and configures the parameters of the hardware synchronization.

  • Page 61: Bios Menu Screen & Function Keys

    4-2 BIOS Menu Screen & Function Keys In the above BIOS Setup main menu of, you can see several options. We will explain these options step by step in the following pages of this chapter, but let us first see a short description of the function keys you may use here: ●...

  • Page 62: Getting Help

    4-3 Getting Help Status Page Setup Menu / Option Page Setup Menu Press F1 to pop up a help window that describes the appropriate keys to use and the possible selections for the highlighted item. To exit the Help Window, press <Esc>. 4-4 Menu Bars There are six menu bars on top of BIOS screen: Main To change system basic configuration...

  • Page 63: Main

    4-5 Main Main menu screen includes some basic system information. Highlight the item and then use the <+> or <-> and numerical keyboard keys to select the value you want in each item. System Date Set the Date. Please use [Tab] to switch between data elements. System Time Set the Time.

  • Page 64: Advanced

    4-6 Advanced Boot Configuration Please refer section 4-6-1 SOC Config Configuration Please refer section 4-6-2 SIO F81804 Please refer section 4-6-3 NVM Express information Please refer section 4-6-4...

  • Page 65: Boot Configuration

    4-6-1 Boot Configuration To select Power-on state for NumLock, default is <off>...

  • Page 66: Soc Configuration Configuration

    4-6-2 SOC Config Configuration ACPI Settings Please refer section 4-6-2-1 CPU Power Limit Configuration Please refer section 4-6-2-2 System Agent (SA) Configuration Please refer section 4-6-2-3 PCH-IO Configuration Please refer section 4-6-2-4 PCH-FW Configuration Please refer section 4-6-2-5...

  • Page 67: Acpi Settings

    4-6-2-1 ► ACPI Settings ACPI S3 Support To enable BIOS support security device or not, default is Enabled.
  • Page 68 4-6-2-2 ► CPU Power Limit Configuration The setting follows INTEL Celeron J6412 CPU power limit default configuration.
  • Page 69 The setting follows INTEL Atom x6413E power limit default configuration.
  • Page 70 Power Limit Override Eenable / disable PL1 / PL2 and enter the power numerical value from 0 to 20000 to get higher or lower CPU TDP...

  • Page 71: System Agent (Sa) Configuration

    4-6-2-3 ► System Agent (SA) Configuration...
  • Page 72 Boot Display Priority First Boot Display To select First Boot Display priority, there are eDP, DDI1 HDMI, DDI2 HDMI, default is eDP Second Boot Display To select Second Boot Display priority, there are DDI1 HDMI, DDI2 HDMI, default is DDI1 HDMI Third Boot Display To select Third Boot Display priority, there is DDI2 HDMI...

  • Page 73: Pch-Io Configuration

    4-6-2-4 ► PCH-IO Configuration PCI Express Configuration Please refer section 4-6-2-4-1 SATA Configuration Please refer section 4-6-2-4-2...

  • Page 74: Pci Express Configuration

    4-6-2-4-1 ► PCI Express Configuration...
  • Page 76 To select NGFF2 device enabled or not and to change the PCIe Speed, there are Auto, Gen1, Gen2, Gen3, default is Auto...
  • Page 77 To select NGFF1 device enabled or not and to change the PCIe Speed, there are Auto, Gen1, Gen2, Gen3, default is Auto...

  • Page 78: Sata Configuration

    4-6-2-4-2 ► SATA Configuration To select SATA port & NGFF2 M.2 SATA device enabled or not.

  • Page 79: Pch-Fw Configuration

    4-6-2-5 ► PCH-FW Configuration...

  • Page 80: Sio F81804

    4-6-3 SIO F81804 UART Port 1 Configuration Please refer section 4-6-3-1 UART Port 2 Configuration Please refer section 4-6-3-2 Hardware Monitor Please refer section 4-6-3-3 Restore on Power Loss Please refer section 4-6-3-4...
  • Page 81 4-6-3-1 ► UART Port 1 Configuration To Enable Serial port or not, default is Enabled.
  • Page 82 Base I/O Address, default is 3F8h.
  • Page 83 Interrupt, default is IRQ4.
  • Page 84 Peripheral, to select the Serial port to RS232 / RS422 / RS485, default is RS232.

  • Page 85: Uart Port 2 Configuration

    4-6-3-2 ► UART Port 2 Configuration To Enable Serial port or not, default is Enabled.
  • Page 86 Base I/O Address, default is 2F8h.
  • Page 87 Interrupt, default is IRQ3.
  • Page 88 Peripheral, to select the Serial port to RS232 / RS422 / RS485, default is RS232.

  • Page 89: Hardware Monitor

    4-6-3-3 ► Hardware Monitor Press [Enter] to view PC health status. This section shows the status of your CPU, Fan, and overall system. This is only available when there is Hardware Monitor function onboard.

  • Page 90: Restore On Power Loss

    4-6-3-4 Restore On Power Loss To select the power behavior after power fail, default is last state.

  • Page 91: Nvm Express Information

    4-6-4 NVM Express Information Press [Enter] to view the NVMe storage devices information.

  • Page 92: Security

    4-7 Security TrEE Protocol Version There are 1.0 and 1.1 versions. TPM Availability To select TPM available or hidden TPM Operation...
  • Page 93 To select TPM operations...

  • Page 94: Set Supervisor Password

    Set Supervisor Password To set up an Supervisor password...

  • Page 95: Power

    4-8 Power Wake On LAN1 To select S3, S5 or S3 / S5 wake on LAN1, default is Disabled. Wake On USB To select S3 wake on USB, default is Disabled. Wake On RTC The optional settings are: Disabled (default), By every day, By day of month.

  • Page 96: Boot

    4-9 Boot Quiet Boot The optional settings are: Enabled (default), Disabled. Network Stack The optional settings are: Enabled, Disabled (default). EFI Boot Device Priority Determine which EFI storage device for booting, this item will not show on this page if there is no any storage device found.

  • Page 97: Save & Exit

    4-10 Save & Exit Exit Saving Changes Save configuration and reset Exit Discarding Changes Reset without saving the changes Load Optimal Defaults To restore the optimal default for all the setup options...

  • Page 98: How To Update Insyde Bios

    STEP 3. Copy the latest BIOS for your LEX motherboard from our website to your bootable disc. STEP 4. (Here take 2I640HL as an example, please enter your motherboard’s name) Insert your bootable disc into X: (X could be C:, A: or others.

  • Page 99: Appendix B: Resolution List

    Appendix B: Resolution list 640 x 480 x ( 256 / 16bit / 32bit ) 800 x 600 x ( 256 / 16bit / 32bit ) 1024 x 768 x ( 256 / 16bit / 32bit ) 1152 x 864 x ( 256 / 16bit / 32bit ) 1280 x 600 x ( 256 / 16bit / 32bit ) 1280 x 720 x ( 256 / 16bit / 32bit ) 1280 x 768 x ( 256 / 16bit / 32bit )