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6.2.33
PEG_CAPL - PCI Express-G Capability List
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Enumerates the PCI Express capability structure.
Table 56.
PEG_CAPL - PCI Express-G Capability List Register
Default
Bit
Access
Value
15:8
RO
7:0
RO
6.2.34
PEG_CAP - PCI Express-G Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Indicates PCI Express device capabilities.
Table 57.
PEG_CAP - PCI Express-G Capabilities Register
Default
Bit
Access
15
RO
14
RO
13:9
RO
8
RW-O
7:4
RO
®
TM
Intel
Core
i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
Datasheet Addendum
112
RST/
PWR
00h
Core
Pointer to Next Capability (PNC)
This value terminates the capabilities list. The Virtual Channel
capability and any other PCI Express specific capabilities that are
reported via this mechanism are in a separate capabilities list
located entirely within PCI Express Extended Configuration
Space.
10h
Core
Capability ID (CID)
Identifies this linked list item (capability structure) as being for
PCI Express registers.
RST/
Value
PWR
0b
Core
Reserved
0b
Core
Reserved
Reserved for TCS Routing Supported.
00h
Core
Interrupt Message Number (IMN)
Not Applicable or Implemented. Hard wired to 0.
1b
Core
Slot Implemented (SI)
0 = The PCI Express Link associated with this port is connected
1 = The PCI Express Link associated with this port is connected
BIOS Requirement: This field must be initialized appropriately
if a slot connection is not implemented.
4h
Core
Device/Port Type (DPT)
hard wired to 4h to indicate root port of PCI Express Root
Complex.
0/6/0/PCI
A0-A1h
0010h
RO
16 bits
Description
0/6/0/PCI
A2-A3h
0142h
RO; RW-O
16 bits
Description
to an integrated component or is disabled.
to a slot.
®
®
Celeron
Processor P4505, U3405 Series
Processor Configuration Registers
August 2010
Document Number: 323178-003
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