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M30245 Group
2.7 Frequency synthesizer (PLL)
This paragraph explains the registers setting method and the notes related to the frequency synthesizer
(PLL circuit).
2.7.1 Overview
The frequency synthesizer generates the 48MHz clock that is necessary for the USB block and the f
clock. These clocks are a multiple of the external input standard clock f(X
frequency synthesizer circuit block diagram.
f(X
)
IN
Prescaler
FSP
(03DE
)
16
Figure 2.7.1. Frequency synthesizer circuit block diagram
(1) Related Registers
Figure 2.7.2 shows a memory location diagram for the frequency synthesizer related registers; Fig-
ures 2.7.3 and 2.7.4 show the composition of the frequency synthesizer related registers.
000A
03DB
03DC
03DD
03DE
03DF
Figure 2.7.2. Memory map of frequency synthesizer related registers
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
f
PIN
Frequency
Multiplier
FSM
(03DD
)
16
16
Protect register (PRCR)
16
Frequency synthesizer clock control register (FSCCR)
16
Frequency synthesizer control register (FSC)
16
Frequency synthesizer multiply register (FSM)
16
Frequency synthesizer prescaler register (FSP)
Frequency synthesizer divide register (FSD)
16
page 121 of 354
f
VCO
LS
FSC
(03DF
(03DC
)
16
Data Bus
2. Frequency synthesizer (PLL)
). Figure 2.7.1 shows the
IN
f
USB
EN
USBC5
Frequency
Divider
8 Bit
FSD
FSCCR
)
16
(03DB
SYN
f
SYN
FSCCR0
)
16
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