Address Space And Timeout Monitoring; Ahb Bus Monitoring; Apb Bus Monitoring; Emif Monitoring - Siemens Ertec 400 Manual

5.3

Address Space and Timeout Monitoring

Monitoring mechanisms are incorporated in the ERTEC 400 for detection of incorrect addressing, illegal
accesses, and timeout. The following I/O are monitored:
AHB bus
•
APB bus
•
EMIF
•
PCI slave
•
5.3.1

AHB Bus Monitoring

Separate address space monitoring is assigned to each of the three AHB masters. If an AHB master addresses
an unused address space, the access is acknowledged with an error response and an FIQ interrupt is triggered at
the ARM946 interrupt controller. The incorrect access address is stored in the QVZ_AHB_ADR system control
register and the associated access type (read, write, HTRANS, HSIZE) is stored in the QVZ_AHB_CTRL system
control register. The master that caused the access error is stored in the QVZ_AHB_M system control register.
In the case of an access violation by PCI or LBU as an AHB master, an interrupt request is also enabled and
stored in the IRT macro. The interrupt is issued to the PCI/LBU bus as an INTA_N interrupt. In the case of an
access violation by the PCI user, Bit 0 (for write accesses) or Bit 1 (for read accesses) is set in the AHB status
register of the PCI bridge and the INTA_N interrupt is enabled.
If more than one AHB master causes an access violation simultaneously (accurate within one AHB clock cycle),
only the violation of the highest priority AHB master is indicated in the registers (see Section 3.1.1).
Diagnostic registers QVZ_AHB_ADR, QVZ_AHB_CTRL, and QVZ_AHB_M remain locked for subsequent
access violations until the QVZ_AHB_CTRL register has been read.
5.3.2

APB Bus Monitoring

The APB address space is monitored on the APB bus. If incorrect addressing is detected in the APB address
space, access to the APB side and AHB side is terminated with an "OKAY" response because the APB bus does
not recognize response-type signaling. An FIQ interrupt is triggered on the ARM945 interrupt controller. The
incorrect access address is placed in the QVZ_APB_ADR system control register. The QVZ_APB_ADR system
control register is locked for subsequent address violations until it has been read.
5.3.3

EMIF Monitoring

In the case of the EMIF, the external RDY_PER_N ready signal is monitored. In order to enable monitoring,
"Extended_Wait_Mode" must be switched on in the Async_Bank_0_Config to Async_Bank_3_Config
configuration registers. If one of the four memory areas that are selected via the CS_PER0_N to CS_PER3_N
chip select outputs is addressed, the memory controller of the ERTEC 400 waits for the RDY_PER_N input
signal. The monitoring duration is set in the ASYNC_WAIT_CYCLE_CONFIG EMIF register and is active if
timeout monitoring (Bit 7) is set in the EXTENDED_CONFIG EMIF register. The specified value (maximum of
255) multiplied by 16 AHB clock cycles yields the monitoring time, i.e., the time that the memory controller waits
for the Ready signal. After this time elapses, a Ready signal is generated for the memory controller and an FIQ
interrupt is generated for the ARM946 interrupt controller. In addition, the address of the incorrect access is stored
in the QVZ_EMIF_ADR system control register. The QVZ_EMIF_ADR system control register is locked for
subsequent address violations until it has been read.
The set FIQ interrupt is then removed if timeout monitoring is reset.
5.3.4

PCI Slave Monitoring

The HREADY signal of the PCI slave is monitored with an 8-bit wide counter, i.e., monitoring is triggered after 256
AHB clock cycles. Monitoring can be enabled or disabled in the PCI_RES_REQ system control register. The
monitoring counter is reset when HREADY = 1 and incremented when HREADY = 0.
There are three possible reasons for the timeout:
Actual timeout in the slave
•
If HREADY is still 0 after a maximum of 255 AHB clock cycles, access to the master is terminated with
an error response and the timeout interrupt is activated.
Access to the slave continues. As long as the slave does not supply HREADY=1, all other accesses to
the slave must be blocked with an error response. The interrupt is triggered only once.
If the address phase of a non-IDLE access is pending in parallel to the extended data phase, this access
is canceled and an IDLE address phase is output to the slave.
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Technical data subject to change
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ERTEC 400 Manual
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