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The following download modes are supported:
BOOT[2]
0
0
0
0
1
1
1
1
Table 8: Selection of Download Source
Booting from NOR Flash or EEPROM with 8/16/32-bit data width via EMIF I/O Bank 0 (CSPER_0_N).
Booting from serial EEPROMs/Flashes via the SPI interface. The GPIO[22] control cable is used as the chip
select for the serial BOOT ROM. The storage medium is selected by means of the GPIO[23] control cable.
Booting from PCI slave interface or a host processor system via the LBU bus.
Booting from UART1. With the bootstrap method, a routine for operation of the serial interface is first
downloaded. This routine then controls the actual program download.
During the boot operation, the address area of the communication RAM from 0x10100000 to 0x1010102F is
reserved for the boot sequence. During the boot sequence, the IRT switch can only be assigned in the area
0x10101030 to 0x1012FFFF.
4.1.1
Booting from External ROM
This boot mode is provided for applications for which the majority of the user firmware runs on the ARM946E-S.
4.1.2
Booting via SPI
SPI-compatible EEPROMs as well as SPI-compatible Data Flash memories can be used as an SPI source. GPIO
cable GPIO[23] is used to select the type.
GPIO[23] = 0
•
GPIO[23] = 1
•
The serial protocols by Motorola, Texas Instruments, and NSC are supported in principle.
Caution:
If an image, that is booted via SPI interface, does not contain any Read-Write data (i.e. only Read-Only data), the
checksum is not calculated properly and the image is not started.
Workaround:
Define at least one global variable so that the image always contains Read-Write data.
4.1.3
Booting via UART1
The UART interface is set at a fixed baud rate of 115200 baud during the boot operation. The boot loader
performs the serial download of the second-level loader to the USER RAM. The USER RAM is mapped to
address 0x00000000 and the second-level loader is started. The second-level loader downloads the user
firmware to the various memory areas of the ERTEC 400 and starts the firmware once the download is complete.
4.1.4
Booting via PCI or LBU
Booting of user software via PCI must be actively performed from an external PCI master. For this purpose, the
PCI slave macro is enabled during the boot operation in the ARM946E-S. This enables the user software to be
loaded from the PCI master to the various memory areas of the ERTEC 400. At the end of the data transfer, the
PCI master sets an identification bit in the SRAM in order to communicate to the ARM processor that the
download is complete.
An external host can perform a boot via the LBU the same as via the PCI. The primary difference lies in the larger
memory area available for selection via the PCI interface.
The PCI/LBU selection is made via the system control register CONFIG_REG.
Note:
Under very rare conditions, in PCI-boot mode, it is possible that the interrupt bit 4 "INT_QVZ_PCI_STATE " in
register "PLL_STAT_REG" will be left "on" after finishing the 1st level boot.
Workaround:
Copyright © Siemens AG 2010. All rights reserved.
Technical data subject to change
BOOT[1]
BOOT[0]
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
SPI-compatible Data Flash
SPI-compatible EEPROM
MEANING
External ROM/NOR Flash 8-bit data width
External ROM/NOR Flash 16-bit data width
External ROM/NOR Flash 32-bit data width
Reserved
Reserved
SPI (e.g. EEPROMS with ser. interface)
UART1
(bootstrap method)
PCI slave/LBU interface (from ext. host)
e.g., AT45DB011B
e.g., AT25HP256
Page
34
ERTEC 400 Manual
Version 1.2.2
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