Xilinx System Generator V2.1 Simulink Manuals

Manuals and User Guides for Xilinx System Generator V2.1 Simulink. We have 1 Xilinx System Generator V2.1 Simulink manual available for free PDF download: Reference Manual

Xilinx System Generator V2.1 Reference Manual

Xilinx System Generator V2.1 Reference Manual (148 pages)

Xilinx Inc. Portable Generator User Manual

Brand: Xilinx | Category: Software | Size: 1 MB

Table of Contents

About this Manual
2
Table of Contents
5
Chapter 1 Introduction

8
Chapter 2 Xilinx Blockset Overview

15
- What Is a Xilinx Block
  15
- Instantiating Xilinx Blocks Within a Simulink Model
  16
- The Block Parameters Dialog Box
  16
- The Nature of Signals in the Xilinx Blockset
  16
- Use of Xilinx Smart-IP Cores by the System Generator
  18
  - Licensed Cores
    18
  - Xilinx Logicore Versions
    19
- Common Options in Block Parameters Dialog Box
  19
  - Arithmetic Type
    20
  - Implement with Xilinx Smart-IP Core (if Possible)
    20
  - Generate Core
    20
  - Latency
    20
  - Precision
    21
  - Number of Bits
    21
  - Overflow and Quantization
    21
  - Override with Doubles
    21
  - Sample Period
    22
Chapter 3 Xilinx Blocks

23
- Basic Elements
  23
  - System Generator
    23
  - Addressable Shift Register
    26
  - Black Box
    28
  - Concat
    30
  - Constant
    31
  - Convert
    31
  - Counter
    32
  - Delay
    35
  - Down Sample
    36
  - Get Valid Bit
    37
  - Mux
    38
  - Parallel to Serial
    39
  - Register
    40
  - Reinterpret
    42
  - Serial to Parallel
    43
  - Set Valid Bit
    45
  - Slice
    45
  - Sync
    47
  - Up Sample
    50
- Communication
  52
  - Convolutional Encoder
    52
  - Depuncture
    54
  - Interleaver Deinterleaver
    55
  - Puncture
    58
  - RS Decoder
    59
  - RS Encoder
    63
  - Viterbi Decoder
    68
- Dsp
  70
  - CIC
    70
  - Dds
    73
  - Fft
    75
  - Fir
    79
- Math
  81
  - Accumulator
    81
  - Addsub
    83
  - Cmult
    84
  - Inverter
    85
  - Logical
    86
  - Mult
    88
  - Negate
    90
  - Relational
    90
  - Scale
    92
  - Shift
    92
  - Sinecosine
    93
  - Threshold
    95
- Matlab I/O
  96
  - Gateway Blocks
    96
  - Enabled Subsystems
    96
  - Gateway in
    97
  - Gateway out
    99
  - Quantization Error Blocks
    101
  - Display
    101
- Memory
  102
  - Dual Port RAM
    102
  - Fifo
    106
  - Rom
    107
  - Single Port RAM
    110
- State Machine
  114
  - Mealy State Machine
    114
  - Moore State Machine
    116
  - Registered Mealy State Machine
    119
  - Registered Moore State Machine
    123
Chapter 4 System Generator Software Features

127
- Using the System Generator Installer
  127
  - Uninstalling Previous System Generator Directories
    127
  - Installed System Generator Directory
    128
- Using Black Boxes
  128
  - Example Model
    129
  - Black Box Window
    129
- Use of Mixed Language Projects
  130
  - Incorporating Mixed Language Black Boxes
    130
- Tips for Creating a High Performance Design
  132
- Using the System Generator Constraints Files
  133
  - System Clock Period
    133
  - Multicycle Path Constraints
    133
  - IOB Timing and Placement Constraints
    134
  - Example for Showing Constraints Use
    134
  - Important Issues
    136
- Files Automatically Created by System Generator
  137
Chapter 5 Using the Xilinx Software

139
- Xilinx ISE 4.1I Project Navigator
  139
- Using an EDIF Software Flow
  143
- Simulation
  143
  - Compiling Your IP
    143
  - Associating Modelsim with ISE 4.1I Project Navigator
    144
- Xilinx Software Tools Resources
  145
Chapter 6 Auxiliary Files

146
- Demonstration Designs
  146
- Perl Scripts
  147

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