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Figure 8. Layer 3 PSB Source Synchronous Signals
4.1.3.1.
Source Synchronous Signal Length Matching Constraints
The routing guidelines presented in the following subsections define the recommended routing
topologies, trace width and spacing geometries, and absolute minimum and maximum routed lengths for
each signal group, which are recommended to achieve optimal SI and timing. In addition to the absolute
length limits provided in the individual guideline tables, more restrictive length matching requirements
called length-matching constraints. These additional requirements further restrict the minimum to
maximum length range of each signal group with respect to strobe, within the overall boundaries defined
in the guideline tables, as required to guarantee adequate timing margins. The amount of minimum to
maximum length variance allowed for each group around the strobe reference length varies from signal
group to signal group depending on the amount of timing variation, which can be tolerated.
4.1.3.2.
Package Length Compensation
The Intel Pentium M / Intel Celeron M processor package length does not need to be accounted for in
the motherboard routing since the processor has the source synchronous signals and the strobes length
matched within the group inside the package routing. However trace length matching of the GMCH
package length does need to be accounted for in the motherboard routing since the package does not
have the source synchronous signals and the strobes length matched within the group inside the package
routing. See Table 8 for the processor and the GMCH package lengths. Skew minimization requires
GMCH die-pad to processor pin (pad-to-pin) trace length matching of the PSB source synchronous
signals that belong to the same group including the strobe signals of that group.
Package length compensation should not be confused with length matching. Length matching refers to
constraints on the min and max length bounds of a signal group based on clock length, whereas package
length compensation refers to the process of compensating for package length variance across a signal
group. There is some overlap in that both affect the target length of an individual signal. Intel
recommends that the initial route be completed based on the length matching formulas in conjunction
®
Intel
855GM/855GME Chipset Platform Design Guide
Intel Pentium M/Celeron M Front Side Bus Design Guidelines
43
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