Memory Signal Description; Memory Topology Guidelines; Ddr3 Channel Signal Groups; Memory Channel Signals Groups Routing - Intel Quark SoC X1000 Design Manual

• Compensation
• Voltage Reference Rules
3.2

Memory Signal Description

Table 6.

DDR3 Channel Signal Groups

Clock Signal Group
DDR3_CK[0], DDR3_CKB[0]
DDR3_CK[1], DDR3_CKB[1]
Control Signal Group (signals per rank)
DDR3_CSB[1:0]
DDR3_CKE[1:0]
DDR3_ODT[1:0]
Command Signal Group (common across ranks)
DDR3_MA[15:0]
DDR3_BS[2:0]
DDR3_RASB
DDR3_CASB
DDR3_WEB
Data Signal Group (common across ranks)
DDR3_DQ[15:0]
DDR3_DQS[0], DDR3_DQSB[0]
DDR3_DQS[1], DDR3_DQSB[1]
Miscellaneous
DDR3_DRAMRSTB
Table 7.

Memory Channel Signals Groups Routing

Parameter
Motherboard Topology
Reference Plane
Note: It is recommended that all of the signals have solid GND referencing planes on both
sides. Minimize the size of void if there are voids on reference planes.
3.3

Memory Topology Guidelines

This chapter presents the various DDR3 topologies possible with Intel
X1000 platforms and associated constraints for PCB layout.
Note: The SoC package length is labeled as "P1" and available in the Trace Length Calculator.
Refer to CDI #523409.
®
Intel Quark™ SoC X1000
PDG
30
Signal Name
Clock Control
Differential-Pair
Point-to-Point
Point-to-Point
Dual Referenced Dual Referenced
GND & PWR GND & PWR
®
Intel Quark™ SoC X1000—DDR3 Memory Design Guidelines
Description
Differential Clock pair for Rank0
Differential Clock pair for Rank1
Chip Select (One per rank)
Clock Enable (One per rank)
On-Die Termination Enable (One per rank)
Memory Address Bus
Bank Select
Row Address Select
Column Address Select
Write Enable
Data Bus
Data Strobe for DQ[7:0]
Data Strobe for DQ[15:8]
Reset for all DRAM devices
Command
Point-to-Point Point-to-Point
Dual Referenced Dual Referenced
GND & PWR GND & PWR
Data Data Strobe
Differential-Pair
Point-to-Point
Dual Referenced
GND & PWR
®
Quark™ SoC
June 2014
Order Number: 330258-002US