Control Signals Routing Guidelines - Intel 80331 Design Manual

Intel® 80331 I/O Processor Design Guide
Memory Controller
Table 44.

Control Signals Routing Guidelines

Reference Plane
Preferred Topology
Breakout Trace WIdth and Spacing
Trace Impedance
Strip Line Trace Spacing (edge to edge)
Series Resistor Rs
Parallel Resistor Rp
Package Trace Length:
Breakout Trace Length (TL1):
Lead-in to Connector Trace Length (TL2):
Parallel Termination Route Length (TL3):
Length Matching Requirements:
Routing Guideline 1
Routing Guideline 2
86
Parameter Routing Guideline
Route over unbroken ground plane is preferred.
(Refer to Table for alternatives if this is not feasible).
Micro-strip only for Un-buffered memory
configurations
Either Micro-strip or Stripline for Buffered DIMMs and
lightly loaded Un-buffered DIMMs (i.e. single bank or
dual bank w/ less than or equal to 36pF input
capacitance).
5 mils x 5 mils acceptable through pin field and
terminations
• 45 ohms Motherboard/Add-in card impedance
• 50 ohms Motherboard/Add-in Card Impedance
• Spacing within group 12 mils minimum
• 5 mils acceptable through pin field and
terminations
• > 20 mils from the Clock/DQ/DQS groups
No series termination required
51.1 +/- 5% ohms
OR
Split termination of 100 ohms +/- 5% terminated to
2.5V and 100 ohms +/- 5% terminated to ground
Place Vtt terminations in a Vtt island after the DIMM
See Table 37 for package net length report and
Table 45 for more details.
≤ 0.5"
2.0" to 9.0"
0.15" to 0.5"
The package lengths from Die to Ball provided in
Table 37 must be accounted for when length matching
For total capacitive loads greater than 36pF, all
ADD/CMD/CTRL trace lengths must be 2.0" to 3.0"
shorter than M_CK's trace length
For total capacitive loads less than or equal to 36pF,
all ADD/CMD/CTRL trace lengths must be 1.0" to 3.0"
shorter than M_CK's trace length
Route these signals on the same layer as the M_CKs.
Minimize layer changes (two vias or less)