Clock Generation; Intel ® 820 Chipset Platform System Clocks - Intel VC820 - Desktop Board Motherboard Design Manual

Chipset
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Clocking
4.1

Clock Generation

There are two clock generator components required in an Intel
Direct Rambus
the CK133 component generates clocks for the rest of the system. Clock synthesizers that meet the
Intel CK98 Clock Specification are suitable for an Intel
generates the clocks listed in
®
Table 4-1. Intel
820 Chipset Platform System Clocks
Number
4
3
8
4
2
1
2
The CK133 is a mixed voltage component. Some of the output clocks are 3.3V and some of the
output clock are 2.5V. As a result, the CK133 device requires both 3.3V and 2.5V. These power
supplies should be a clean as possible. Noise in the power delivery system for the clock driver can
cause noise on the clock lines.
The MCH uses the same clock for hub interface and AGP. It is important that the
hub interface/AGP clocks are routed to ensure the skew requirements are met between:
The MCH hub interface/AGP clock and the AGP connector (or device)
®
Intel
820 Chipset Design Guide
*
Clock Generator (DRCG) generates clock for the Direct Rambus
Table
4-1.
Name on
Used for
CK133
CPUCLK[0-3]
System Bus Clock
APIC[0-2]
APIC Bus Clock
PCI Bus Clock
PCI, LPC, FWH Flash
BIOS Bus Clock
PCICLK[1-7,F]
FWH Flash BIOS
Interface Clock
LPC Interface Clock
Hub Interface/AGP Bus
Clock
Hub Interface Clock
3V66[0-3]
AGP Bus Clock
Unused
Internal ICH Logic
REF[0-1]
Internal Super I/O Logic
48 MHz
USB
DRCG Reference Clock
CPU_DIV2[0-1]
Unused
®
820 chipset based system. The
®
820 chipset based system. The CK133
Name on
Routed to
Receiver
2 Processors
CLK
MCH
HCLKIN
ITP
BCLK
2 Processors
PICCLK
ICH
APICCLK
5 PCI
CLK
Devices
ICH
PCICLK
FWH Flash
CLK
BIOS
LPC
CLK
MCH
CLK66
ICH
CLK66
AGP device/
CLK
slot
N/A
N/A
ICH
CLK14
Vendor
Super I/O
Specific
ICH
CLK48
DRCG
REFCLK
N/A
N/A
Clocking
4
*
interface while
Frequency
Voltage
100/133 MHz 2.5V
33 MHz
2.5V
33 MHz
3.3V
66 MHz
3.3V
14 MHz
3.3V
48 MHz
3.3V
50/66 MHz
2.5V
4-1

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