Intel ® Quark™ Soc X1000 Power-Up Sequence - Intel Quark SoC X1000 Design Manual

Platform Power Delivery Requirements—Intel
®
Figure 48. Intel Quark™ SoC X1000 Power-up Sequence
ALWAYS ON
(**when
platform
power
available)
SUSPEND
(low power)
CORE
June 2014
Order Number: 330258-002US
®
Quark™ SoC X1000
TM
Intel® Quark SoC X1000 rails (platform implementation may vary)
VCC3P3_S5
VCC1P0_S5
(Externally derived)
VCC1P8_S5
(internal-derived using SLDO)
VCC1P5_S5
VCC3P3_S3
VCC1P0_S3
(internal-derived using SLDO)
VCC1P8_S3
(internal-derived using SLDO)
VCC1P5_S3
VCC3P3_S0
VCC1P05_S0
(internal-derived using SLDO)
VCC1P8_S0
(internal-derived using SLDO)
VCC1P0_S0
VCC1P5_S0
Core/S0 Rails: 3; Suspend/S3 Rails: 2; S5 Rails: 3; RTC: 1:
S5_PG
3mS
S3_PG
4mS
S0_1P0_PG
§ §
S0_PG
®
Intel Quark™ SoC X1000
PDG
99