Dmax_Curr_X_Count Mdma_Yy_Curr_X_Count Registers - Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual

DMA Registers
Table 5-14. Inner Loop Count Register Memory-mapped Addresses
Register Name
DMA0_X_COUNT
DMA1_X_COUNT
DMA2_X_COUNT
DMA3_X_COUNT
DMA4_X_COUNT
DMA5_X_COUNT
DMA6_X_COUNT
DMA7_X_COUNT
DMA8_X_COUNT
DMA9_X_COUNT
DMA10_X_COUNT
DMA11_X_COUNT
MDMA_D0_X_COUNT
MDMA_S0_X_COUNT
MDMA_D1_X_COUNT
MDMA_S1_X_COUNT
DMAx_CURR_X_COUNT/MDMA_yy_CURR_X_COUNT Registers
The current inner loop count register (
), shown in
X_COUNT
in the current DMA row (inner loop). On the first memory transfer of
each DMA work unit, it is loaded with the value in the
ister and then decremented. For 2D DMA, on the last memory transfer in
each row except the last row, it is reloaded with the value in the
register; this occurs at the same time that the value in the
COUNT
CURR_Y_COUNT
5-86
Memory-mapped Address
0xFFC0 0C10
0xFFC0 0C50
0xFFC0 0C90
0xFFC0 0CD0
0xFFC0 0D10
0xFFC0 0D50
0xFFC0 0D90
0xFFC0 0DD0
0xFFC0 0E10
0xFFC0 0E50
0xFFC0 0E90
0xFFC0 0ED0
0xFFC0 0F10
0xFFC0 0F50
0xFFC0 0F90
0xFFC0 0FD0
Figure 5-12, holds the number of transfers remaining
register is decremented. Otherwise it is decremented each
ADSP-BF537 Blackfin Processor Hardware Reference
DMAx_CURR_X_COUNT/MDMA_yy_CURR_
DMAx_X_COUNT
reg-
DMAx_X_
DMAx_