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MB90420/5 (A) SERIES F
23.6.8 Transmission Request Register (TREQR)
Transmission request register (TREQR) stores transmission requests to the message buffers (x) or displays
their state.
n Transmission request register (TREQR)
Address: 000043
(CAN0)
H
Address: 000073
(CAN1)
H
Read/write →
Initial value →
Address: 000042
(CAN0)
H
Address: 000072
(CAN1)
H
Read/write →
Initial value →
When 1 is written to TREQx, transmission to the message buffer (x) starts. If RFWTx of the remote frame
receiving wait register (RFWTR)*1 is 0, transmission starts immediately.
transmission starts after waiting until a remote frame is received (RRTRx of the remote request receive
register (RRTRR)*1 becomes 1). Transmission starts*2 immediately even when RFWTx = 1, if RRTRx is
already 1 when 1 is written to TREQx.
*1: For RFWTR and TRTRR, see Sections 23.6.9 and 23.6.10.
*2: For cancellation of transmission, see Sections 23.6.11 and 23.6.12.
Writing 0 to TREQx is ignored.
0 is read when a read-modify-write instruction is performed.
If clearing (to 0) at completion of the transmit operation and setting by writing 1 are concurrent, clearing is
preferred.
If 1 is written to more than one bit, transmission is performed from the lower-numbered message buffer (x).
TREQx is 1 while transmission is in the wait state, and becomes 0 when transmission is completed or
canceled.
23.6.9 Transmission RTR Register (TRTRR)
This register stores the RTR (Remote Transmission Request) bits for the message buffers (x).
n Transmission RTR register (TRTRR)
Address: 003C0B
(CAN0)
H
Address: 003D0B
(CAN1)
H
Read/write →
Initial value →
Address: 003C0A
(CAN0)
H
Address: 003D0A
(CAN1)
H
Read/write →
Initial value →
0: Data frame transmitted
1: Remote frame transmitted
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
15
14
13
TREQ15
TREQ14
TREQ13
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
7
6
5
TREQ7
TREQ6
TREQ5
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
15
14
13
TRTR15
TRTR14
TRTR13
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
7
6
5
TRTR7
TRTR6
TRTR5
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
23-20
12
11
10
TREQ12
TREQ11
TREQ10
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
4
3
2
TREQ4
TREQ3
TREQ2
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
12
11
10
TRTR12
TRTR11
TRTR10
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
4
3
2
TRTR4
TRTR3
TRTR2
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
← Bit No.
9
8
TREQ9
TREQ8
(R/W)
(R/W)
(0)
(0)
← Bit No.
1
0
TREQ1
TREQ0
(R/W)
(R/W)
(0)
(0)
However, if RFWTx = 1,
← Bit No.
9
8
TRTR9
TRTR8
(R/W)
(R/W)
(0)
(0)
← Bit No.
1
0
TRTR1
TRTR0
(R/W)
(R/W)
(0)
(0)
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