Hardware Interrupt; Table 6-7 Mechanism Related To Hardware Interrupt - Fujitsu MB90420/5 (A) Series Hardware Manual

6.4 Hardware Interrupt

The hardware interrupt responds to the interrupt request signals from a resource, suspends the program
executed by the CPU and transfers control to the interrupt processing program defined by user.
2
EI OS and the external interrupt are also executed as a kind of hardware interrupt.
n Hardware interrupt
• Function of hardware interrupt
The hardware interrupt compares the interrupt level of the interrupt request signal output by the resource
and the interrupt level mask register (ILM) in the processor status (PS) of the CPU and refers the value of
the I flag in the processor status (PS) by hardware to determine whether the interrupt is accepted or not.
When the hardware interrupt is accepted, the registers in the CPU are automatically saved in the system
stack, the currently requested interrupt level is stored in the interrupt level mask register (ILM), and then a
branch is performed to the corresponding interrupt vector.
• Multiple interrupt
A multiple hardware interrupt can be started.
• EI
2
OS
2
EI OS has an auto transfer function between memory and I/O, and starts the hardware interrupt at
completion of transfer. EI
other interrupt requests and EI
• External interrupt
The external interrupt (wake-up interrupt included) is accepted as a hardware interrupt by means of the
resource (interrupt request detector).
• Interrupt vector
The interrupt vector tables referred during interrupt handling are allocated to FFFC00
are shared by the software interrupt.
For the allocation of interrupt number and the interrupt vector, see Section 6.2.
n Mechanism of hardware interrupt
The mechanism related to the hardware interrupt consists of the four sections shown in Table 6-7. When
using the hardware interrupt, these four sections must be set by the program.
Resource
Interrupt controller
CPU
FFFC00 to
H
FFFFFF in memory
H
2
OS is not be started in the multiple mode; during processing of a certain EI
2
OS requests are all suspended.

Table 6-7 Mechanism Related to Hardware Interrupt

Mechanism Concerning Hardware
Interrupt
Interrupt enable bit, interrupt request bit
Interrupt control register (ICR)
Interrupt enable flag (I)
Interrupt level mask register (ILM)
Microcode
Interrupt vector table
INTERRUPT
Controls interrupt request issued from resource
Sets interrupt level and controls EI
Identifies interrupt enable state
Compares requested interrupt level and current
interrupt level
Executes interrupt-processing routine
Stores branch destination address at interrupt
handling
6-13
to FFFFFF
H
Function
2
OS
2
OS,
, and
H