Table 7-12 Lcd Interface Timing - 4-Bit Single And 8-Bit Single/Dual Monochrome Panel - Epson S1D13503 Series Technical Manual

EPSON

Table 7-12 LCD Interface Timing - 4-Bit Single and 8-Bit Single/Dual Monochrome Panel

Symbol
t
LP period (single panel mode)
1
t
LP period (dual panel mode)
1
t
YD hold from LP falling edge (AUX[01] bit 5 = 0)
2
t
YD hold from LP falling edge (AUX[01] bit 5 = 1)
2
t
LP pulse width (AUX[01] bit 5 = 0)
3
t
LP pulse width (AUX[01] bit 5 = 1)
3
t
WF delay from LP falling edge
4
t
LP setup to XSCL falling edge
5
(AUX[01] bit 5 = 0 and AUX[03] bit 2 = 0)
t
LP hold from XSCL falling edge
6a
(AUX[01] bit 5 = 0 and AUX[03] bit 2 = 0)
t
LP hold from XSCL falling edge
6a
(AUX[01] bit 5 = 0 and AUX[03] bit 2 = 1)
t
XSCL falling edge to LP falling edge - single panel mode
6b
(AUX[01] bit 5 = 1 and AUX[03] bit 2 = 0)
t
XSCL falling edge to LP falling edge - single panel mode
6b
(AUX[01] bit 5 = 1 and AUX[03] bit 2 = 1)
t
XSCL falling edge to LP falling edge - dual panel mode
6c
(AUX[01] bit 5 = 1 and AUX[03] bit 2 = 0)
t
XSCL falling edge to LP falling edge - dual panel mode
6c
(AUX[01] bit 5 = 1 and AUX[03] bit 2 = 1)
t
LP falling edge to XSCL falling edge
7a
(AUX[01] bit 5 = 0 and AUX[03] bit 2 = 0)
t
LP falling edge to XSCL falling edge
7a
(AUX[01] bit 5 = 0 and AUX[03] bit 2 = 1)
t
LP falling edge to XSCL falling edge
7b
(AUX[01] bit 5 = 1 and AUX[03] bit 2 = 0)
t
LP falling edge to XSCL falling edge
7b
(AUX[01] bit 5 = 1 and AUX[03] bit 2 = 1)
t
XSCL period (AUX[03] bit 2 = 0)
8
t
XSCL period (AUX[03] bit 2 = 1)
8
t
XSCL high width (AUX[03] bit 2 = 0)
9
t
XSCL high width (AUX[03] bit 2 = 1)
9
t
XSCL low width (AUX[03] bit 2 = 0)
10
t
XSCL low width (AUX[03] bit 2 = 1)
10
t
UD[3:0], LD[3:0] setup to XSCL falling edge (AUX[03] bit 2 = 0)
11
t
UD[3:0], LD[3:0] setup to XSCL falling edge (AUX[03] bit 2 = 1)
11
t
UD[3:0], LD[3:0] hold from XSCL falling edge (AUX[03] bit 2 = 0)
12
t
UD[3:0], LD[3:0] hold from XSCL falling edge (AUX[03] bit 2 = 1)
12
t
LP falling edge to XSCL rising edge (AUX[01] bit 5 = 1)
13
Where t = 1/f
OSC
where HT = (number of horizontal panel pixels) ∗ t
where HNDP = horizontal non-display period in units of t
details).
** -10ns for 5V operation, -24ns for 3.0V and 3.3V operation.
1-26
Parameter
= input (pixel) clock period,
OSC
4-Bit Single
Min. Max.
HT + HNDP –
- 10
n/a –
t
8 - 10 –
OSC
t
13 - 10 –
OSC
t
6 - 5 –
OSC
t
5 - 5 –
OSC
0 20
n/a –
t
2 - 5 –
OSC
t
- 5 –
OSC
t
13 - 5 –
OSC
t
12 - 5 –
OSC
n/a –
n/a –
t
2 - 5 –
OSC
t
- 5 –
OSC
t
7 - 5 –
OSC
t
6 - 5 –
OSC
t
4 - 5 –
OSC
t
2 - 5 –
OSC
t
2 - 5 –
OSC
t
- 5 –
OSC
t
2 - 10 –
OSC
t
- 10 –
OSC
t
2 - 10** –
OSC
t
- 10** –
OSC
t
2 - 10 –
OSC
t
- 10 –
OSC
t
5 - 5 –
OSC
,
OSC
(see Section 9.3 on page 57 for
OSC
8-Bit Single/Dual
Units
Min. Max.
HT + HNDP – ns
- 10
2 ∗ (HT +
– ns
HNDP) - 10
t
8 - 10 – ns
OSC
t
13 - 10 – ns
OSC
t
6 - 5 – ns
OSC
t
5 - 5 – ns
OSC
0 20 ns
t
2 - 5 – ns
OSC
t
4 - 5 – ns
OSC
t
2 - 5 – ns
OSC
t
15 - 5 – ns
OSC
t
13 - 5 – ns
OSC
t
31 - 5 – ns
OSC
t
29 - 5 – ns
OSC
t
4 - 5 – ns
OSC
t
2 - 5 – ns
OSC
t
9 - 5 – ns
OSC
t
7 - 5 – ns
OSC
t
8 - 5 – ns
OSC
t
4 - 5 – ns
OSC
t
4 - 5 – ns
OSC
t
2 - 5 – ns
OSC
t
4 - 10 – ns
OSC
t
2 - 10 – ns
OSC
t
4 - 10** – ns
OSC
t
2 - 10** – ns
OSC
t
4 - 10 – ns
OSC
t
2 - 10 – ns
OSC
t
5 - 5 – ns
OSC
S18A-A-011-01