Single Monochrome 4-Bit Panel Timing; Figure 7-19: Single Monochrome 4-Bit Panel Timing - Epson S1D13504 Technical Manual

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7.4.3 Single Monochrome 4-Bit Panel Timing

FPFRAME
FPLINE
MOD
UD[3:0], UD[3:0]
FPLINE
MOD
FPSHIFT
UD3
UD2
UD1
UD0
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 320x240 panel
VDP = Vertical Display Period
VNDP = Vertical Non-Display Period
HDP = Horizontal Display Period
HNDP = Horizontal Non-Display Period
S1D13504
X19A-A-002-19
VDP
LINE1 LINE2 LINE3 LINE4
1-1 1-5
1-2 1-6
1-3 1-7
1-4 1-8

Figure 7-19: Single Monochrome 4-Bit Panel Timing

= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1
= (REG[0Ah] bits [5:0]) + 1
= ((REG[04h] bits [6:0]) + 1)*8Ts
= ((REG[05h] bits [4:0]) + 1)*8Ts
Epson Research and Development
VNDP
LINE239 LINE240
HDP
Vancouver Design Center
LINE1 LINE2
HNDP
1-317
1-318
1-319
1-320
Hardware Functional Specification
Issue Date: 01/11/06