Table 15-1: Power Save Mode Function Summary - Epson S1D13706 Technical Manual

Epson Research and Development
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15 Power Save Mode
Note
Hardware Functional Specification
Issue Date: 01/11/13
A software initiated Power Save Mode is incorporated into the S1D13706 to accommodate
the need for power reduction in the hand-held devices market. This mode is enabled via the
Power Save Mode Enable bit (REG[A0h] bit 0).
Software Power Save Mode saves power by powering down the panel and stopping display
refresh accesses to the display buffer.

Table 15-1: Power Save Mode Function Summary

IO Access Possible?
Memory Writes Possible?
Memory Reads Possible?
Look-Up Table Registers Access Possible?
Sequence Controller Running?
Display Active?
LCD I/F Outputs
GPIO Pins configured for HR-TFT/D-TFD
GPIO Pins configured as GPIOs Access Possible?
1
When power save mode is enabled, the memory controller is powered down and the
status of the memory controller is indicated by the Memory Controller Power Save Sta-
tus bit (REG[A0h] bit 3). However, memory writes are possible during power save
mode because the S1D13706 dynamically enables the memory controller for display
buffer writes.
2
GPIO Pins are configured using the configuration pin CNF3 which is latched on the
rising edge of RESET#. For information on CNF3, see Table 4-8: "Summary of Power-
On/Reset Options," on page 29.
3
GPIOs can be accessed and if configured as outputs can be changed.
After reset, the S1D13706 is always in Power Save Mode. Software must initialize the chip
(i.e. programs all registers) and then clear the Power Save Mode Enable bit.
PWMCLK
2
Software
Normal
Power Save
Yes
1
Yes
1
No
Yes
No
No
Forced Low Active
Stopped Active
Forced Low Active
2 3
Yes
Page 149
Yes
Yes
Yes
Yes
Yes
Yes
Yes
S1D13706
X31B-A-001-08