Power Save Mode Function Summary; Pin States In Power Save Modes; Table 13-1: Power Save Mode Function Summary; Table 13-2: Pin States In Power Save Modes - Epson S1D13504 Technical Manual

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13.3 Power Save Mode Function Summary

Display Active?
Register Access Possible?
Memory Access Possible?
Host Bus Interface Running?
Memory Interface Running?

13.4 Pin States in Power Save Modes

LCD outputs
LCDPWR
DRAM outputs
CRT / DAC outputs
Host Interface outputs
S1D13504
X19A-A-002-19

Table 13-1: Power Save Mode Function Summary

Function
Note
(1) except for RAMDAC registers.
(2) Yes if CBR suspend mode refresh is selected.

Table 13-2: Pin States in Power Save Modes

Pins
Active
On
Active
Active
Active
Note
1. FPFRAME and FPLINE are forced to their inactive states as defined by REG[0Ch] bit 6
and REG[07h] bit 6 respectively.
2. Selectable: may be CBR refresh, self-refresh or no refresh at all.
3. DACWR#, DACRD#, DACRS0, DACRS1 are active but DACCLK is disabled.
4. Active for non-DAC register access only.
Power Save Mode (PSM)
Normal Software
(Active) Suspend
Yes No
Yes Yes (1)
Yes No
Yes Yes
Yes No (2)
Pin State
Normal Software
(Active) Suspend
Forced Low (1)
Off
Refresh Only (2)
Disabled (3)
Active (4)
Epson Research and Development
Vancouver Design Center
Hardware
Suspend
No
No
No
No
No (2)
Hardware
Suspend
Forced Low (1)
Off
Refresh Only (2)
Disabled (3)
Disabled
Hardware Functional Specification
Issue Date: 01/11/06