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4.2 S1D13706 Hardware Configuration
S1D13706
Pin Name
CNF[2:0]
CNF3
CNF4
CNF5
CNF[7:6]
4.3 Register/Memory Mapping
Note
Interfacing to the PC Card Bus
Issue Date: 01/02/23
The S1D13706 uses CNF7 through CNF0 to allow selection of the bus mode and other
configuration data on the rising edge of RESET#. For details on configuration, refer to the
S1D13706 Hardware Functional Specification, document number X31B-A-001-xx.
The following table shows the configuration required for this implementation of a
S1D13706 to PC Card bus interface.
Table 4-1: Summary of Power-On/Reset Configuration Options
value on this pin at the rising edge of RESET# is used to configure: (1/0)
1
100 = Generic #2 Host Bus Interface
GPIO pins as inputs at power on
Big Endian bus interface
Active high WAIT#
see Table 4-2: "CLKI to BCLK Divide Selection" for recommended setting
= configuration for PC Card Bus
Table 4-2: CLKI to BCLK Divide Selection
CNF7
CNF6
0
0
0
1
1
0
1
1
= recommended setting for PC Card Bus
The S1D13706 is a memory mapped device. The S1D13706 uses two 128K byte blocks
which are selected using A17 from the PC Card bus (A17 is connected to the S1D13706
M/R# pin). The internal registers occupy the first 128K byte block and the 80K byte display
buffer occupies the second 128K byte block.
The PC Card socket provides 64M bytes of memory address space. However, the
S1D13706 only needs a 256K byte block of memory to accommodate its 80K byte display
buffer and register set. For this reason, only address bits A[17:0] are used while A[25:17]
are ignored. The S1D13706's memory and registers are aliased every 256K bytes for a total
of 256 times in the 64M byte PC Card memory address space.
If aliasing is not desirable, the upper addresses must be fully decoded.
GPIO pins as HR-TFT / D-TFT outputs
Little Endian bus interface
Active low WAIT#
CLKI to BCLK Divide
1:1
2:1
3:1
4:1
Page 13
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S1D13706
X31B-G-005-02
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