Register/Memory Mapping - Epson S1D13505F00A Technical Manual

1: INTERFACING THE S1D13505 TO THE PC CARD BUS
The following diagram demonstrates a typical implementation of the interface.
PC Card socket
OE#
WE#
CE1#
CE2#
RESET
A[25:0]
D[15:0]
WAIT#
Figure 1-1 Schematic for S1D13505 in PC Card Bus

Register/Memory Mapping

The PC Card socket provides 64M byte of address space. The S1D13505 is a memory mapped
device; 2M byte Display Buffer, and 47 byte Internal Register Set.
Table 1-1 shows a typical implementation having the Chip Select pin (CS#) connected to ground
(always enabled) and the Memory/Register Select pin (M/R#) connected to Address bit A21. This
provides the following decoding:
Table 1-1 Register/Memory Mapping Typical Implementation
M/R#
CS#
(A21)
0 0
0 1 200000h - 3FFFFFh
Note: The internal register set only requires 47 bytes. Therefore, without further resolution on the decode
select logic (M/R# connected to A21), the entire register set is aliased for every 64 byte boundary
within the specified address range above. Since address bits A25 to A22 are ignored, the S1D13505
registers and display memory are aliased sixteen times. If aliasing is not desirable, the upper ad-
dresses must be fully decoded.
5-2
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15K
Oscillator
Address Range
0 - 1FFFFFh
Internal Register Set decoded
Display Buffer decode
EPSON
S1D13505
RD#
WE0#
RD/WR#
WE1#
RESET#
V
DD
BS#
CS#
A21
M/R#
A[20:0]
AB[20:0]
DB[15:0]
WAIT#
BUSCLK
CLKI
Function
1
APPLICATION NOTES (X23A-G-005-05)