Ram Access (Ram_Wrdoor); Fifo Access (Register Access); Fifo Access (Dma) - Epson S2R72V18 Technical Manual

1. Functions
FIFO data can be read out from the RAM_Rd register as required, regardless of FIFO area settings.
The RAM_RdAdrs_H,L and RAM_RdCount register values are updated in sequence while the
RAM_Rd function runs. These registers should not be accessed after the RAM_Rd function starts
until the CPU_IntStat.RAM_RdCmp bit has been set. Values read out from these registers are not
guaranteed while the RAM_Rd function runs. Writing to these registers may result in malfunctions.
1.6.5.2

RAM Access (RAM_WrDoor)

To write to the FIFO using the RAM_WrDoor_0,1 registers, set the initial write address in the
RAM_WrAdrs_H,L registers and write the data using the RAM_WrDoor_0,1 register. The
RAM_WrAdrs_H,L registers are incremented automatically by the data quantity written for each
access, allowing continuous writing to the RAM_WrDoor_0,1 registers when writing data to
continuous addresses.
FIFO data can be written to the FIFO using the RAM_WrDoor_0,1 registers, regardless of FIFO
area settings.
1.6.5.3

FIFO Access (Register Access)

To read data from FIFO by register access, set AREAx{x=0-5}Join_0.JoinCPU_Rd to 1 for one
area, then read using the FIFO_Rd_0,1 or FIFO_ByteRd registers.
To write data to the FIFO by register access, set AREAx{x=0-5}Join_0.JoinCPU_Wr to 1 for one
area, then write using the FIFO_Wr_0,1 or FIFO_ByteWr registers.
The FIFO_RdRemain_H,L registers indicate the remaining data quantity that can be read from
FIFO for a single area set using JoinCPU_Rd. Similarly, the FIFO_WrRemain_H,L registers
indicate the remaining area for writing to the FIFO for a single area set using JoinCPU_Wr.
Note that data will be read from FIFO during register dumping if either JoinCPU_Rd bit is set for
register dumping when debugging the firmware using ICE.
1.6.5.4

FIFO Access (DMA)

To read from FIFO using CPU DMA access, the AREAx{x=0-5}Join_0.JoinDMA bit is set for one
area, then the DMA_Control.Dir bit is set to 1, and the data is read out by DMA procedures.
To write to the FIFO using CPU DMA access, the AREAx{x=0-5}Join_0.JoinDMA bit is set for
one area for each DMA channel, then the DMA_Control.Dir bit is set to 0, and the data is written by
DMA procedures.
The DMA_Remain_H,L registers indicate the remaining data size that can be read from FIFO for
the single area selected by the AREAx{x=0-5}Join_0.JoinDMA bit for each DMA channel. It also
indicates the remaining space available for writing in the FIFO for the single area selected by the
AREAx{x=0-5}Join_0.JoinDMA bit for each DMA channel.
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EPSON
S2R72V18 Technical Manual (Rev.1.00)