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7.1.4 Generic MPU Interface Synchronous Timing
T
BCLK
BCLK
t1
A[20:0]
M/R#
t1
t2
CS#
t1
t2
RD0#,RD1#
WE0#,WE1#
t4
Hi-Z
WAIT#
Hi-Z
D[15:0](write)
t9
Hi-Z
D[15:0](read)
S1D13504
X19A-A-002-19
t2
t7
Figure 7-4: Generic MPU Interface Synchronous Timing
Epson Research and Development
Valid
t5
Valid
t10
Valid
Vancouver Design Center
t2
t1
t1
t2
t3
t1
t2
t6
Hi-Z
t8
Hi-Z
t11
Hi-Z
Hardware Functional Specification
Issue Date: 01/11/06