Miscellaneous Registers - Epson S1D13505F00A Technical Manual

8: REGISTERS

Miscellaneous Registers

Miscellaneous Disable Register
REG[1Bh]
Host Interface
n/a
Disable
bit 7 Host Interface Disable
This bit is set to 1 during power-on/reset.
This bit must be programmed to 0 to enable the Host Interface. When this bit is high, all
memory and all registers except REG[1Ah] (read-only) and REG[1Bh] are inaccessible.
bit 0 Half Frame Buffer Disable
This bit is used to disable the Half Frame Buffer.
When this bit = 1, the Half Frame Buffer is disabled.
When this bit = 0, the Half Frame Buffer is enabled.
When a single panel is selected, the Half Frame Buffer is automatically disabled and this
bit has no effect.
The half frame buffer is needed to fully support dual panels. Disabling the Half Frame
Buffer reduces memory bandwidth requirements and increases the supportable pixel
clock frequency, but results in reduced contrast on the LCD panel (the duty cycle of the
LCD is halved). This mode is not normally used except under special circumstances such
as simultaneous display on a CRT and dual panel LCD. When this mode is used the Alter-
nate Frame Rate Modulation scheme should be used (see REG[31h]). For details on
Frame Rate calculation see Section 14.2, "Frame Rate Calculation".
MD Configuration Readback Register 0
REG[1Ch]
MD[7] Status MD[6] Status MD[5] Status
MD Configuration Readback Register 1
REG[1Dh]
MD[15] Status MD[14] Status MD[13] Status MD[12] Status MD[11] Status MD[10] Status MD[9] Status
REG[1Ch] bits 7–0 MD[15:0] Configuration Status
REG[1Dh] bits 7–0 These are read-only status bits for the MD[15:0] pins configuration status at
the rising edge of RESET#. MD[15:0] are used to configure the chip at the
rising edge of RESET# – see "Pin Descriptions and Summary of Configura-
tion Options" for details.
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n/a n/a n/a
MD[4] Status MD[3] Status MD[2] Status
EPSON
S1D13505F00A HARDWARE FUNCTIONAL
RW
Half Frame
n/a n/a
Buffer Disable
RO
MD[1] Status MD[0] Status
RO
MD[8] Status
SPECIFICATION (X23A-A-001-12)