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8.3.7 Miscellaneous Registers
Power Save Configuration Register
REG[A0h]
Vertical Non-
Display
Period Status
(RO)
7
6
bit 7
bit 3
bit 0
Reserved
REG[A1h]
7
6
bit 0
S1D13706
X31B-A-001-08
n/a
5
Vertical Non-Display Period Status
This is a read-only status bit.
When this bit = 0, the LCD panel output is in a Vertical Display Period.
When this bit = 1, the LCD panel output is in a Vertical Non-Display Period.
Memory Controller Power Save Status
This read-only status bit indicates the power save state of the memory controller.
When this bit = 0, the memory controller is powered up.
When this bit = 1, the memory controller is powered down and the MCLK source can be
turned off.
Note
Memory writes are possible during power save mode because the S1D13706 dynamical-
ly enables the memory controller for display buffer writes.
Power Save Mode Enable
When this bit = 1, the software initiated power save mode is enabled.
When this bit = 0, the software initiated power save mode is disabled.
At reset, this bit is set to 1. For a summary of Power Save Mode, see Section 15, "Power
Save Mode" on page 149.
Note
Memory writes are possible during power save mode because the S1D13706 dynamical-
ly enables the memory controller for display buffer writes.
5
Reserved.
This bit must remain at 0.
Memory
Controller
Power Save
Status (RO)
4
3
n/a
4
3
Epson Research and Development
Vancouver Design Center
Read/Write
Power Save
n/a
Mode Enable
2
1
Read/Write
2
1
Hardware Functional Specification
Issue Date: 01/11/13
0
Reserved
0
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