Fifo Control (Fifoctl) R/W; Fifo Data(Fifodata) R/W; Non Dma Transfer Size (Ndmasiz) R/W - Epson S1R72105 Technical Manual

7.3.39 FIFO Control (FIFOCTL) R/W

Used for clearing the SCSI-FIFO data and for checking its status.
Address Register Name
31h FIFOCTL
BIT7,6,5,4,3 RESERVED
BIT2 CLEAR FIFO
Setting this bit to HIGH clears data stored in SCSI-FIFO.
The bit returns to LOW automatically after clearing.
BIT1 FULL
When this bit is HIGH it means that SCSI-FIFO is full. In this state, any data written into SCSI-FIFO is ignored.
BIT0 EMPTY
When this bit is HIGH it means that SCSI-FIFO is empty. In this state, any attempt to read data from SCSI-FIFO
results in invalid data read out.
7.3.40 FIFO Data (FIFODATA) R/W
This register allows access to SCSI-FIFO from the CPU.
Address Register Name
32h FIFODATA

7.3.41 Non DMA Transfer Size (NDMASIZ) R/W

This register sets the number of bytes of data transfer in Non-DMA mode. In Read mode, the register allows
to read out the size of data yet to be transferred.
Address Register Name
33h NDMASIZ
Rev.1.0
Bit Symbol
7: -
6: -
5: -
4: -
3: -
2: FCLR
1: FULL
0: EMPTY
Bit Symbol
7: FD7
6: FD6
5: FD5
4: FD4
3: FD3
2: FD2
1: FD1
0: FD0
Bit Symbol
7: NSZ7
6: NSZ6
5: NSZ5
4: NSZ4
3: NSZ3
2: NSZ2
1: NSZ1
0: NSZ0
EPSON
S1R72105 Technical Manual
Description
CLEAR FIFO
FIFO FULL
FIFO EMPTY
Description
(MSB)
SCSI_FIFO data
(LSB)
Description
(MSB)
Non DMA Transfer Size
(LSB)
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