Lcap - Link Capabilities; Lcap - Link Capabilities Register - Intel I5-520E - DATASHEET ADDENDUM Datasheet

Processor Configuration Registers
Table 60. DSTS - Device Status Register
Bit Access
2 RWC
1 RWC
0 RWC
6.2.38

LCAP - Link Capabilities

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Indicates PCI Express device specific capabilities.
Table 61. LCAP - Link Capabilities Register (Sheet 1 of 3)
Default
Bit Access
Value
31:24 RO
23:22 RO
April 2010
Document Number: 323178-002
Default RST/
Value PWR
0b Core
0b Core
0b Core
RST/
PWR
03h Core Port Number (PN)
Indicates the PCI Express port number for the given PCI Express
link. Matches the value in Element Self Description[31:24].
00b Core Reserved
® TM
Intel Core i7-620LE/UE, i7-610E, i5-520E and Intel
Description
Fatal Error Detected (FED)
When set this bit indicates that fatal error(s) were
detected. Errors are logged in this register regardless of
whether error reporting is enabled or not in the Device
Control register. When Advanced Error Handling is
enabled, errors are logged in this register regardless of
the settings of the uncorrectable error mask register.
Non-Fatal Error Detected (NFED)
When set this bit indicates that non-fatal error(s) were
detected. Errors are logged in this register regardless of
whether error reporting is enabled or not in the Device
Control register.
When Advanced Error Handling is enabled, errors are
logged in this register regardless of the settings of the
uncorrectable error mask register.
Correctable Error Detected (CED)
When set this bit indicates that correctable error(s) were
detected. Errors are logged in this register regardless of
whether error reporting is enabled or not in the Device
Control register.
When Advanced Error Handling is enabled, errors are
logged in this register regardless of the settings of the
correctable error mask register.
0/6/0/PCI
AC-AFh
03214C81h
RO; RW-O
32 bits
Description
®
Celeron
®
Processor P4500, P4505 Series
Datasheet Addendum
115