Pcists6 - Pci Status; Pcists6 - Pci Status Register - Intel CELERON PROCESSOR P4505 - DATASHEET ADDENDUM Datasheet

6.2.4

PCISTS6 - PCI Status

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register reports the occurrence of error conditions associated with primary side of
the "virtual" Host-PCI Express bridge embedded within the processor.
Table 27. PCISTS6 - PCI Status Register (Sheet 1 of 2)
Bit Access Default
Value
15 RO
14 RWC
13 RO
12 RO
11 RO
10:9 RO
8 RO
7 RO
6 RO
® TM
Intel Core i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
Datasheet Addendum
88
RST/
PWR
0b Core Detected Parity Error (DPE)
Not Applicable or Implemented. Hard wired to 0. Parity
(generating poisoned TLPs) is not supported on the primary side
of this device (we don't do error forwarding).
0b Core Signaled System Error (SSE)
This bit is set when this Device sends an SERR due to detecting
an ERR_FATAL or ERR_NONFATAL condition and the SERR Enable
bit in the Command register is 1. Both received (if enabled by
BCTRL6[1]) and internally detected error messages do not affect
this field.
0b Core Received Master Abort Status (RMAS)
Not Applicable or Implemented. Hard wired to 0. The concept of a
master abort does not exist on primary side of this device.
0b Core Received Target Abort Status (RTAS)
Not Applicable or Implemented. Hard wired to 0. The concept of a
target abort does not exist on primary side of this device.
0b Core Signaled Target Abort Status (STAS)
Not Applicable or Implemented. Hard wired to 0. The concept of a
target abort does not exist on primary side of this device.
00b Core DEVSELB Timing (DEVT)
This device is not the subtractively decoded device on bus 0. This
bit field is therefore hard wired to 00 to indicate that the device
uses the fastest possible decode.
0b Core Master Data Parity Error (PMDPE)
Because the primary side of the PCIe graphic's virtual P2P bridge
is integrated with the PROCESSOR functionality there is no
scenario where this bit will get set. Because hardware will never
set this bit, it is impossible for software to have an opportunity to
clear this bit or otherwise test that it is implemented. The PCI
Local Bus Specification defines it as a R/WC, but for our
implementation an RO definition behaves the same way and will
meet all Microsoft testing requirements.
This bit can only be set when the Parity Error Enable bit in the PCI
Command register is set.
0b Core Fast Back-to-Back (FB2B)
Not Applicable or Implemented. Hard wired to 0.
0b Core Reserved
Processor Configuration Registers
0/6/0/PCI
6-7h
0010h
RO; RWC
16 bits
Description
® ®
Celeron Processor P4505, U3405 Series
August 2010
Document Number: 323178-003