Table of Contents
Advertisement
7.
PCI Configuration Registers
The 82559ER acts as both a master and a slave on the PCI bus. As a master, the 82559ER interacts
with the system main memory to access data for transmission or deposit received data. As a slave,
some 82559ER control structures are accessed by the host CPU to read or write information to the
on-chip registers. The CPU also provides the 82559ER with the necessary commands and pointers
that allow it to process receive and transmit data.
7.1
LAN (Ethernet) PCI Configuration Space
The 82559ER PCI configuration space is configured as 16 Dwords of Type 0 Configuration Space
Header, as defined in the PCI Specification, Revision 2.1. A small section is also configured
according to its device specific configuration space. The configuration space header is depicted
below in
Figure
BIST
Max_Lat
Power Management Capabilities
Reserved
7.1.1
PCI Vendor ID and Device ID Registers
The Vendor ID and Device ID of the 82559ER are both read only word entities. Their HARD-
CODED values are:
Vendor ID: 8086H
Device ID: 1209H
Datasheet
17.
Device ID
Status
Class Code
Header Type
CSR Memory Mapped Base Address Register
CSR I/O Mapped Base Address Register
Flash Memory Mapped Base Address Register
Reserved Base Address Register
Reserved Base Address Register
Reserved Base Address Register
Reserved
Subsystem ID
Expansion ROM Base Address Register
Reserved
Reserved
Min_Gnt
Data
Figure 17. PCI Configuration Registers
Networking Silicon — GD82559ER
Vendor ID
Command
Revision ID
Latency Timer
Cache Line Size
Subsystem Vendor ID
Cap_Ptr
Interrupt Pin
Interrupt Line
Next Item Ptr
Capability ID
Power Management CSR
00H
04H
08H
0CH
10H
14H
18H
1CH
20H
24H
28H
2CH
30H
34H
38H
3CH
DCH
E0H
47
Advertisement
Table of Contents
