Pvccap2 - Port Vc Capability Register 2; Pvccap1 - Port Vc Capability Register 1 - Intel I5-520E - DATASHEET ADDENDUM Datasheet

Size:
Describes the configuration of PCI Express Virtual Channels associated with this port.
Table 74.

PVCCAP1 - Port VC Capability Register 1

Bit Access
31:12 RO
11:10 RO
9:8 RO
7 RO
6:4 RO
3 RO
2:0 RO
6.3.3

PVCCAP2 - Port VC Capability Register 2

B/D/F/Type:
Address Offset:
Default Value:00000000h
Access: RO;
Size:32 bits
Describes the configuration of PCI Express Virtual Channels associated with this port.
® TM
Intel Core i7-620LE/UE, i7-610E, i5-520E and Intel
Datasheet Addendum
134
Default RST/
Value PWR
00000h Core
00b Core
00b Core
0b Core
000b Core
0b Core
000b Core
®
Celeron
32 bits
Description
Reserved
Reserved
Reserved for Port Arbitration Table Entry Size ():
Reserved
Reserved for Reference Clock ():
Reserved
Low Priority Extended VC Count (LPEVCC):
Indicates the number of (extended) Virtual Channels in
addition to the default VC belonging to the low-priority VC
(LPVC) group that has the lowest priority with respect to
other VC resources in a strict-priority VC Arbitration. The
value of 0 in this field implies strict VC arbitration.
Reserved
Extended VC Count (EVCC):
Indicates the number of (extended) Virtual Channels in
addition to the default VC supported by the device.
0/6/0/MMR
108-10Bh
®
Processor P4500, P4505 Series
Processor Configuration Registers
April 2010
Document Number: 323178-002