Lsts - Link Status; Lsts - Link Status Register - Intel I5-520E - DATASHEET ADDENDUM Datasheet

Table 62. LCTL - Link Control Register (Sheet 3 of 3)
Bit Access Default
Value
1:0 RW
6.2.40

LSTS - Link Status

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Indicates PCI Express link status.
Table 63. LSTS - Link Status Register (Sheet 1 of 3)
Default
Bit Access
Value
15 RWC
® TM
Intel Core i7-620LE/UE, i7-610E, i5-520E and Intel
Datasheet Addendum
120
RST/
PWR
00b Core Active State PM (ASPM)
Controls the level of active state power management supported
on the given link.
00:
01:
10:
11:
Note: "L0s Entry Enabled" indicates the Transmitter entering L0s
is supported. The Receiver must be capable of entering L0s even
when the field is disabled (00b).
ASPM L1 must be enabled by software in the Upstream
component on a Link prior to enabling ASPM L1 in the
Downstream component on that Link. When disabling ASPM L1,
software must disable ASPM L1 in the Downstream component on
a Link prior to disabling ASPM L1 in the Upstream component on
that Link. ASPM L1 must only be enabled on the Downstream
component if both components on a Link support ASPM L1.
RST/
PWR
0b Core Link Autonomous Bandwidth Status (LABWS)
This bit is set to 1b by hardware to indicate that hardware has
autonomously changed link speed or width, without the port
transitioning through DL_Down status, for reasons other than to
attempt to correct unreliable link operation.
This bit must be set if the Physical Layer reports a speed or width
change was initiated by the downstream component that was
indicated as an autonomous change.
This bit must be set when the upstream component receives eight
consecutive TS1 or TS2 ordered sets with the Autonomous
Change bit set.
®
Celeron
Processor Configuration Registers
Description
Disabled
L0s Entry Supported
L1 Entry Enabled
L0s and L1 Entry Supported
0/6/0/PCI
B2-B3h
1000h
RWC; RO
16 bits
Description
®
Processor P4500, P4505 Series
April 2010
Document Number: 323178-002