ST STM32L4 5 Series Reference Manual page 1125

RM0351
32.6.13 TIM16/TIM17 break and dead-time register (TIMx_BDTR)
Address offset: 0x44
Reset value: 0x0000 0000
31 30 29
Res Res Res
15 14 13
MOE AOE BKP BKE
rw rw rw
Note: As the AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits may be write-locked depending on
the LOCK configuration, it may be necessary to configure all of them during the first write
access to the TIMx_BDTR register.
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 MOE: Main output enable
This bit is cleared asynchronously by hardware as soon as the break input is active. It is set
by software or automatically depending on the AOE bit. It is acting only on the channels
which are configured in output.
0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit.
1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in
TIMx_CCER register)
See OC/OCN enable description for more details
enable register (TIM15_CCER) on page
Bit 14 AOE: Automatic output enable
0: MOE can be set only by software
1: MOE can be set by software or automatically at the next update event (if the break input is
not be active)
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bit 13 BKP: Break polarity
0: Break input BRK is active low
1: Break input BRK is active high
Note: 1. This bit can not be modified as long as LOCK level 1 has been programmed (LOCK
Bit 12 BKE: Break enable
0: Break inputs (BRK and CCS clock failure event) disabled
1; Break inputs (BRK and CCS clock failure event) enabled
Note: 1. This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in
28 27 26 25
Res Res Res Res
12 11 10 9
OSSR OSSI LOCK[1:0]
rw rw rw rw
in TIMx_BDTR register).
bits in TIMx_BDTR register).
2. Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
TIMx_BDTR register).
2. Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
General-purpose timers (TIM15/TIM16/TIM17)
24 23 22
Res Res Res
8 7 6
rw rw rw
1100).
DocID024597 Rev 5
21 20 19
Res Res Res Res
5 4 3
DTG[7:0]
rw rw rw
(Section 32.5.8: TIM15 capture/compare
18 17 16
Res Res
2 1 0
rw rw rw
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