ST STM32L4 5 Series Reference Manual page 1111

RM0351
Table 197. TIM15 register map and reset values (continued)
Offset Register
TIM15_CCER
0x20
Reset value
TIM15_CNT
0x24
Reset value 0
TIM15_PSC
0x28
Reset value
TIM15_ARR
0x2C
Reset value
TIM15_RCR
0x30
Reset value
TIM15_CCR1
0x34
Reset value
TIM15_CCR2
0x38
Reset value
TIM15_BDTR
0x44
Reset value
TIM15_DCR
0x48
Reset value
TIM15_DMAR
0x4C
Reset value
TIM15_OR1
0x50
Reset value
General-purpose timers (TIM15/TIM16/TIM17)
0
0
1
0
0
0
0
DocID024597 Rev 5
0
CNT[15:0]
0 0 0 0 0 0 0 0
PSC[15:0]
0 0 0 0 0 0 0 0
ARR[15:0]
1 1 1 1 1 1 1 1
0
CCR1[15:0]
0 0 0 0 0 0 0 0
CCR2[15:0]
0 0 0 0 0 0 0 0
LOCK
[1:0]
0 0 0 0 0 0 0 0
DBL[4:0]
0 0 0 0 0
DMAB[15:0]
0 0 0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
1 1 1 1 1 1 1
REP[7:0]
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
DT[7:0]
0 0 0 0 0 0 0
DBA[4:0]
0 0 0 0 0
0 0 0 0 0 0 0
0 0 0
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