Figure 321. Tim15 Block Diagram - ST STM32L4 5 Series Reference Manual

RM0351
1. The internal break event source can be:
- A clock failure event generated by CSS. For further information on the CSS, refer to
system (CSS)
- A PVD output
- SRAM parity error signal
®
- Cortex -M4 LOCKUP (Hardfault) output
- COMP output

Figure 321. TIM15 block diagram

DocID024597 Rev 5
General-purpose timers (TIM15/TIM16/TIM17)
Section 6.2.10: Clock security
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