Figure 306. Clearing Timx Ocxref - ST STM32L4 5 Series Reference Manual

Advanced arm-based 32-bit mcus

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General-purpose timers (TIM2/TIM3/TIM4/TIM5)

for both values of the OCxCE enable bit. In this example, the timer TIMx is programmed in

In case of a PWM with a 100% duty cycle (if CCRx>ARR), OCxREF is enabled again at the

next counter overflow.

shows the behavior of the OCxREF signal when the ETRF input becomes high,

Figure 306. Clearing TIMx OCxREF

DocID024597 Rev 5

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