ST STM32L4 5 Series Reference Manual page 1092

General-purpose timers (TIM15/TIM16/TIM17)
32.5.3 TIM15 slave mode control register (TIM15_SMCR)
Address offset: 0x08
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 SMS[3]: Slave mode selection - bit 3
Refer to SMS description - bits 2:0.
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 MSM: Master/slave mode
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect
synchronization between the current timer and its slaves (through TRGO). It is useful if we
want to synchronize several timers on a single external event.
Bits 6:4 TS[2:0]: Trigger selection
This bit field selects the trigger input to be used to synchronize the counter.
000: Internal Trigger 0 (ITR0)
001: Internal Trigger 1 (ITR1)
010: Internal Trigger 2 (ITR2)
011: Internal Trigger 3 (ITR3)
100: TI1 Edge Detector (TI1F_ED)
101: Filtered Timer Input 1 (TI1FP1)
110: Filtered Timer Input 2 (TI2FP2)
See
meaning for each Timer.
Note: These bits must be changed only when they are not used (e.g. when SMS=000) to
Bit 3 Reserved, must be kept at reset value.
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28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
Table 195: TIMx Internal trigger connection on page 1093
avoid wrong edge detections at the transition.
DocID024597 Rev 5
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
Res. MSM TS[2:0]
rw rw rw
20 19 18 17
Res. Res. Res. Res.
4 3 2 1
Res. SMS[2:0]
rw rw rw
for more details on ITRx
RM0351
16
SMS[3]
rw
0
rw