ST STM32L4 5 Series Reference Manual page 1129

RM0351
Bit 9 BKINP: BRK BKIN input polarity
This bit selects the BKIN alternate function input sensitivity. It must be programmed together
with the BKP polarity bit.
0: BKIN input is active low
1: BKIN input is active high
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bit 8 BKDF1BK1E: BRK dfsdm1_break[1] enable
This bit enables the dfsdm1_break[1] for the timer's BRK input. dfsdm1_break[1] output is
'ORed' with the other BRK sources.
0: dfsdm1_break[1] input disabled
1: dfsdm1_break[1] input enabled
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bits 7:3 Reserved, must be kept at reset value
Bit 2 BKCMP2E: BRK COMP2 enable
This bit enables the COMP2 for the timer's BRK input. COMP2 output is 'ORed' with the other
BRK sources.
0: COMP2 input disabled
1: COMP2 input enabled
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bit 1 BKCMP1E: BRK COMP1 enable
This bit enables the COMP1 for the timer's BRK input. COMP1 output is 'ORed' with the other
BRK sources.
0: COMP1 input disabled
1: COMP1 input enabled
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bit 0 BKINE: BRK BKIN input enable
This bit enables the BKIN alternate function input for the timer's BRK input. BKIN input is
'ORed' with the other BRK sources.
0: BKIN input disabled
1: BKIN input enabled
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
32.6.18 TIM17 option register 1 (TIM17_OR1)
Address offset: 0x50
Reset value: 0x0000
31 30 29
Res Res Res
15 14 13
Res Res Res
in TIMx_BDTR register).
in TIMx_BDTR register).
in TIMx_BDTR register).
in TIMx_BDTR register).
in TIMx_BDTR register).
28 27 26 25
Res Res Res Res
12 11 10 9
Res Res Res Res
General-purpose timers (TIM15/TIM16/TIM17)
24 23 22
Res Res Res
8 7 6
Res Res Res
DocID024597 Rev 5
21 20 19 18
Res Res Res Res
5 4 3 2
Res Res Res Res
17 16
Res Res
1 0
TI1_RMP[1:0]
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