2.9.11 Icu Register Description; Table 4: Overview Of Interrupt Control Register - Siemens ERTEC200 Manual

PRIOREG 1
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PRIOREG15

Table 4: Overview of Interrupt Control Register

2.9.11 ICU Register Description

IRVEC
Description Interrupt vector register
Input with highest priority pending interrupt request
Bit No. Name
3:0 IRVEC
31:4 Vector ID
FIVEC
Description Fast interrupt vector register
Number of the highest-priority pending fast interrupt request
Bit No. Name
2:0 FIVEC
31:3 Vector ID
LOCKREG
Description Priority lock register
Specification of a priority for blocking interrupt requests of lower and equal priority
Bit No. Name
3 – 0 LOCKPRIO
7 LOCKENABLE
FIQ1SREG
Description Fast interrupt request 1 select register
Declaration of an IRQ input as FIQ6 (input FIQ6 on FIQ interrupt controller)
Bit No. Name
3 – 0 FIQ1SREG
7 FIQ1SENABLE
FIQ2SREG
Description Fast interrupt request 2 select register
Declaration of an IRQ input as FIQ7 (input FIQ7 on FIQ interrupt controller)
Bit No. Name
3 – 0 FIQ2SREG
7 FIQ2SENABLE
IRQACK
Description Interrupt vector register with IRQ acknowledge
Confirmation of highest-priority pending interrupt request by reading
the associated interrupt vector
Bit No. Name
3 – 0 IRVEC
31 - 4 Vector ID
Copyright © Siemens AG 2007. All rights reserved.
Technical data subject to change
0x0074 4 bytes
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0x00AC 4 bytes
R
Description
For pending, valid interrupt: Binary code of input number.
Default vector: Bit[3:0] = 1
For pending, valid interrupt: Bit[31:4] = 0.
Default vector: Bit[31:4] = 1
R
Description
For pending, valid interrupt: Binary code of FIQ number.
Default vector: Bit[2:0] = 1
For pending valid Bit[31:3] = 0.
Default vector: Bit[31:3] = 1
R/W
Description
Binary code of lock priority.
0=Lock inactive / 1=Lock active
R/W
Description
Number of the input to be selected (binary code)
0=Ignore FIQ declaration
0=Take into account FIQ declaration
R/W
Description
Number of the input to be selected (binary code)
0=Ignore FIQ declaration
0=Take into account FIQ declaration
R
Description
Binary code of input number
Valid IRQ vector: always '0'.
Default vector: always '1' (also bits 3 – 0).
R/W 0x0000000F
R/W 0x0000000F
Addr.: 0x5000_0000
Addr.: 0x5000_0004
Addr.: 0x5000_0008
Addr.: 0x5000_000C
Addr.: 0x5000_0010
Addr.: 0x5000_0014
27
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Priority register 15
Default: 0xFFFF_FFFF
Default: 0xFFFF_FFFF
Default: 0x0000_0000
Default: 0x0000_0000
Default: 0x0000_0000
Default: 0xFFFF_FFFF
ERTEC 200 Manual
Version 1.1.0