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®
®
Intel
Pentium
M Processor and Intel
I/O Controller Hub 3 (Intel
Table 84.
LCI Routing Parameter Summary
Parameter
Trace Impedance (Z
Trace Spacing
Termination
Length Tuning
Figure 119.
LAN_CLK Routing Example
9.7.2
General LAN Routing Guidelines and Considerations
9.7.2.1
General Trace Routing Considerations
Trace routing considerations are important to minimize the effects of crosstalk and propagation
delays on sections of the board where high-speed signals exist. Signal traces should be kept as short
as possible to decrease interference from other signals, including those propagated through power
and ground planes. Observe the following suggestions to help optimize board performance:
•
Maintain constant symmetry and spacing between the traces within a differential pair.
•
Keep the signal trace lengths of a differential pair equal to each other.
•
Keep the total length of each differential pair under four inches. (Many customer designs with
differential traces longer than five inches have had one or more of the following issues: IEEE
phy conformance failures, excessive EMI, and/or degraded receive BER [Bit Error Rate].)
•
Do not route the transmit differential traces closer than 100 mils to the receive differential
traces.
•
Do not route any other signal traces parallel to the differential traces, or closer than 100 mils to
the differential traces (300 mils is recommended).
•
Keep maximum separation between differential pairs to 7 mils.
170
®
E7501 Chipset Platform
®
ICH3-S)
60 Ω ± 15% due to signal integrity requirements.
)
0
Minimum of 100 mils from non-LCI signals.
33 Ω series resistor may be installed at the driver side of the interface.
On the motherboard, the length of each data trace should be either equal in length
to the LAN_CLK trace, or up to 0.5 inch shorter than the LAN_CLK trace.
LAN_CLK should always be the longest motherboard trace in each group.
Requirements
LAN_RXD0
LAN_CLK
Design Guide
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