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I/O Subsystem
Figure 67. SMBUS 2.0/SMLink Protocol
Host Controller and
Slave Interface
®
Intel
Intel does not support external access of the ICH4-M's Integrated LAN controller via the SMLink
interface. Also, Intel does not support access of the ICH4-M's SMBus slave interface by the ICH4-M's
SMBus host controller. Refer to the Intel
Datasheet for full functionality descriptions of the SMLink and SMBus interface.
10.6.1.
SMBus Architecture and Design Considerations
10.6.1.1. SMBus Design Considerations
SMBus design solutions will vary for all platforms. The total bus capacitance and device capabilities
must be considered when designing SMBus segments. Routing SMBus to the PCI slots makes the
design process even more challenging since they add so much capacitance to the bus. This extra
capacitance has a large affect on the bus time constant which in turn affects the bus rise and fall times.
Primary considerations in the design process are:
1. Device class (High/Low power). Most designs use primarily high power devices.
2. Are there devices that must run in S3?
3. Amount of V
166
SMBus
ICH4
SMLink
Wire OR
(optional)
_
current available, i.e. minimizing load of V
CC
SUSPEND
®
®
Intel
852GME, Intel
852GMV and Intel
SPD Data
Temperature on
Thermal Sensor
SMBCLK
SMBDATA
SMLink0
SMLink1
Motherboard
LAN
Controller
®
82801DBM I/O Controller Hub 4 Mobile (ICH4-M)
®
852PM Chipset Platforms Design Guide
Network
Interface Card
on PCI Bus
Microcontroller
SMbus-SMlink_IF
_
CC
SUSPEND.
R
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