Rx 64B/66B Block; Functional Description; Ports And Attributes - Xilinx Virtex-6 FPGA User Manual

Chapter 4: Receiver

RX 64B/66B Block

Functional Description

The GTH transceiver implements the 64B/66B block based on IEEE 802.3-2008 Clause 49,
"Physical Sublayer (PCS) for 64B/66B, type 10GBASE-R." The RX 64B/66B block includes
the block synchronization, the gearbox, and the descrambler.

Ports and Attributes

Table 4-15
Table 4-15: RX 64B/66B Block Ports
Port Dir
RXCODEERR0[7:0] Out
RXCODEERR1[7:0]
RXCODEERR2[7:0]
RXCODEERR3[7:0]
122
defines the RX 64B/66B block ports.
Clock Domain
RXUSERCLKIN0 These outputs indicate an error occurred on RXDATA<n> or they
are used as an extension of RXDATA<n> depending on the mode
RXUSERCLKIN1
selected in the receive datapath:
RXUSERCLKIN2
8B/10B: These outputs indicate that RXDATA<n> is the result of
RXUSERCLKIN3
an 8B/10B code error.
RXCODEERR<n>[7] corresponds to RXDATA<n>[63:56]
RXCODEERR<n>[6] corresponds to RXDATA<n>[55:48]
RXCODEERR<n>[5] corresponds to RXDATA<n>[47:40]
RXCODEERR<n>[4] corresponds to RXDATA<n>[39:32]
RXCODEERR<n>[3] corresponds to RXDATA<n>[31:24]
RXCODEERR<n>[2] corresponds to RXDATA<n>[23:16]
RXCODEERR<n>[1] corresponds to RXDATA<n>[15:8]
RXCODEERR<n>[0] corresponds to RXDATA<n>[7:0]
64B/66B: RXCODEERR<n>[0] indicates a 64B/66B code error.
RXCODEERR<n>[7:1] are not used for this mode.
Raw mode: These outputs are used as part of RXDATA<n>[79:72].
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Description
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010