Dynamic Reconfiguration Port - Xilinx Virtex UltraScale+ FPGAs User Manual

Each GTM transceiver features several loopback modes to facilitate testing:
• Near-end PCS Loopback (Path 1 in the above figure). While in Near-end PCS Loopback, the RX
XCLK domain is clocked by the TX parallel clock (TX XCLK).
• Near-end PMA loopback (path 2 in the above figure).
• Far-end PCS Loopback (path 3 in the above figure). The transceiver in far-end PCS loopback
must use the same reference clock used by the transceiver that is the source of the loopbak
data.
Ports and Attributes
The following table defines the loopback ports.
Table 23: Loopback Ports
Port
CH[0/1]_LOOPBACK[2:0]
The following table defines the loopback attributes.
Table 24: Loopback Attributes
Attribute
CH[0/1]_TX_LPBK_CFG0
CH[0/1]_TX_LPBK_CFG1

Dynamic Reconfiguration Port

The dynamic reconfiguration port (DRP) allows the dynamic change of parameters of the
GTM_DUAL primitives. The DRP interface is a processor-friendly synchronous interface with an
address bus (DRPADDR) and separate data buses for reading (DRPDO) and writing (DRPDI)
configuration data to the primitives. An enable signal (DRPEN), a read/write signal (DRPWE), and
a ready/valid signal (DRPRDY) are the control signals that implement read and write operations,
indicate operation completion, or indicate the availability of data.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Clock
Dir
Domain
In Async Loopback control for channel 0/1:
Type
16-bit Reserved. Use the recommended value from the Wizard.
16-bit Reserved. Use the recommended value from the Wizard.
Chapter 2: Shared Features
Description
3'b000: Normal operation.
3'b001: Near-End PCS Loopback.
3'b010: Near-End PMA Loopback.
3'b011: Reserved.
3'b100: Reserved.
3'b101: Reserved.
3'b110: Far-End PCS Loopback.
Description
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