Can Clock (Psclocksource, Psdvc, Canclock) - Fujitsu FR Series Application Note

Chapter 3 User Clock Settings (CLOCKSPEED == CLOCK_USER)
Example:
The base clock frequency is 64 MHz. The CPU clock should run with 64 MHz, the peripheral
with 16 MHz and the external bus clock with 32 MHz.
#set CPUCLOCK
#set PERCLOCK
#set EXTBUSCLOCK

3.5 CAN clock (PSCLOCKSOURCE, PSDVC, CANCLOCK)

The CAN prescaler clock source and source clock divider can be configured in the following.
Main Clock SV
Cntr.
Logic
Main
Oscillator
1
4 MHz
0 CSVCR_
MSVE
Sub
Oscillator
Sub Clock SV
0
32 kHz
1
CSVCR_
SSVE
Cntr.
RC Logic
Oscillator
100 kHz CSVCR
RC
0
Oscillator
1 CSCFG_
2 MHz
RCSEL
Available settings for PSCLOCKSOURCE (CANPRE):
- PSCLOCK_CLKB
- PSCLOCK_PLL
- PSCLOCK_MAIN
The following table shows the selectable prescaler source clock frequency depending on the
selectable PLL multiplier. The frequencies are only valid; if the settings for the PLL
multiplication are the ones, defined above.
- Main clock 4 MHz:
PLL Multiplier
PLLx3
PLLx4
PLLx5
PLLx6
PLLx7
PLLx8
PLLx9
PLLx10
PLLx11
PLLx12
© Fujitsu Microelectronics Europe GmbH
Start91460.asm
0x00 ;<<< 0x486h: DIV0R_B;
0x03 ;<<< 0x486h: DIV0R_P;
0x01 ;<<< 0x487h: DIV1R_T;
1/2
PLL Interface x1, x2, ...x25
1/G
Auto-Gear
PLL
x CLKVCO 1/M
CLKPLLFB 1/N
FB
0
Multiplier
PLLDIVM, PLLDIVG, PLLMULG, PLLCTRL
1
CSVCR_
SCKS
The CLKB is the clock source for the CAN clock prescaler.
The CLKVCO is the clock source for the CAN clock prescaler.
The main oscillation is the clock source for the CAN clock prescaler.
PSCLOCK_CLKB
(CLKB)
12 MHz
16 MHz
20 MHz
24 MHz
28 MHz
32 MHz
36 MHz
40 MHz
44 MHz
48 MHz
CLKPLL
Clock
0
1
Modulator
1
CMCR, CMPR 2
0
CMCR_ 3
FMOD
0
3
1 CANPRE_
CPCKS
PSCLOCK_PLL
(CLKVCO)
144 MHz
160 MHz
160 MHz
144 MHz
112 MHz
128 MHz
144 MHz
160 MHz
88 MHz
96 MHz
- 21 -
=> /1 ; 64 MHz
=> /4 ; 16 MHz
=> /2 ; 32 MHz
Main Oscillation
Sub Oscillation
RC Oscillation 100 kHz
Main Clock / 2
Sub Clock
Φ
Base Clock
Ext. Bus Clock
CLKT
Divider /1 .. /16
DIV1R
Peripheral Clock
CLKR_
CLKP
CLKS
Divider /1 .. /16
DIV0R
CPU Clock
CLKB
Divider /1 .. /16
DIV0R
CAN Clock
CANCLK
Divider /1 .. /16
CANPRE
PSCLOCK_MAIN
(Main Oszillation)
4 MHz
4 MHz
4 MHz
4 MHz
4 MHz
4 MHz
4 MHz
4 MHz
4 MHz
4 MHz
MCU-AN-300021-E-V10